Loading patent…
AssigneeRenesas Technology Corp.
InventorsYoshiki Kawajiri, Masaaki Terasawa, Takanori Yamazoe
Estimating the term…
The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.
A data processing circuit comprising:
Dependencies are inferred from the claim text.