US 7,411,826 B2Granted

Semiconductor integrated circuit device

AssigneeKabushiki Kaisha Toshiba

InventorsMasayuki Ichige, Riichiro Shirota, Kikuko Sugimae

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Abstract

A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.

Claims12

Dependent claims

A memory card comprising:

a flash memory block including
a memory cell array having
a first cell block provided in the memory cell array with a plurality of memory cell strings each of which is configured by a plurality of electrically rewritable memory cells and at least one selection transistor which are serially connected being arranged in the first cell block, and
a second cell block provided in the memory cell array with a plurality of memory cell strings each of which is configured by a plurality of electrically rewritable memory cells different in number from those of the first cell block and at least one selection transistor which are serially connected being arranged in the second cell block, widths of element regions of the memory cell strings of the first cell block being different from those of the second cell block;
and
a controller block which controls the flash memory block, the controller block managing data transfer between the flash memory block and an outside.

3 more elements

A memory card comprising:

a flash memory block including
a memory cell array having
a first cell block provided in the memory cell array with a plurality of memory cell strings each of which is configured by a plurality of electrically rewritable memory cells and at least one selection transistor which are serially connected being arranged in the first cell block, and
a second cell block provided in the memory cell array, a plurality of memory cell strings each of which is configured by a plurality of electrically rewritable memory cells different in number from those of the first cell block and at least one selection transistor which are serially connected being arranged in the second cell block;
and a third cell block provided in the memory cell array, a plurality of memory cell strings each of which is configured by a plurality of electrically rewritable memory cells different in number from those of the first and second cell blocks and at least one selection transistor which are serially connected being arranged in the second cell block;
and
a controller block which controls the flash memory block, the controller block managing data transfer between the flash memory block and an outside.

4 more elements

A memory card comprising:

a flash memory block including
a memory cell array having
a first cell block provided in the memory cell array with a plurality of memory cell strings each of which is configured by a plurality of electrically rewritable memory cells and at least one selection transistor which are serially connected being arranged in the first cell block,
and a second cell block provided in the memory cell array with a plurality of memory cell strings each of which is configured by a plurality of electrically rewritable memory cells different in number from those of the first cell block and at least one selection transistor which are serially connected being arranged in the second cell block, one of the first and second cell blocks in which the number of memory cells of the memory cell string is smaller performing a binary data storage operation, the other of the first and second cell blocks in which the number of memory cells of the memory cell string is larger performing a multi-value data storage operation;
and
a controller block which controls the flash memory block, the controller block managing data transfer between the flash memory block and an outside.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/480,460Filed 5 Jul 2006 · continuation
Priority: JP 2001-37500729 Sep 2001
Published: US 2006/0250849 A19 Nov 2006
Granted: 12 Aug 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
G11C 16/04
Electrically programmable: using variable threshold transistors, e.g. FAMOS
G11C 16/0433
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Family

Application10/256,102Parent of this division · filed 27 Sep 2002
Application11/108,634Parent of this continuation · filed 19 Apr 2005
US 2006/0250849 A1Pre-grant publication · published 9 Nov 2006
US 7,082,055 B2Parent of this continuation
US 6,925,008 B2Parent of this division
Application11/108,634Parent of this division
US 2003/0095448 A1Published application
US 2005/0224894 A1Published application
US 7,411,826 B2This patent

From the US filing history. Foreign family members aren’t listed.

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