Semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• a semiconductor substrate,
• element isolation regions which are arranged at a pitch P on the semiconductor substrate and separate first to third element regions in the semiconductor substrate,
• a first memory cell unit formed in the first element region and having memory cell transistors serially connected between selection transistors,
• a second memory cell unit formed in the second element region and having memory cell transistors serially connected between selection transistors,
• a third memory cell unit formed in the third element region and having memory cell transistors serially connected between selection transistors,
• a first bit line contact formed to extend over the first element region, element isolation region and second element region and commonly connected to one end of a current path of the first memory cell unit and one end of a current path of the second memory cell unit,
• a second bit line contact formed to extend over the third element region and element isolation region and connected to one end of a current path of the third memory cell unit,
• a first source line contact formed to extend over the element isolation region and first element region and connected to the other end of the current path of the first memory cell unit, and
• a second source line contact formed to extend over the second element region, element isolation region and third element region and commonly connected to the other end of the current path of the second memory cell unit and the other end of the current path of the third memory cell unit.