Semiconductor memory device capable of increasing writing speed

A semiconductor memory device comprising:

• a memory cell array having a plurality of memory cells which are arranged in a matrix form and connected in series, the plurality of memory cells being connected with word lines and bit lines;
• a selection transistor which selects the word lines;
• and
• a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, read and erase operations of data with respect to the memory cells,
• wherein the selection transistor is formed on a well, and a first negative voltage is supplied to the well and a first voltage (the first voltage≧the first negative voltage) is supplied to a predetermined non-selected word line in the write operation.

A semiconductor memory device comprising:

• a memory cell array having a plurality of memory cells arranged in a matrix form, the plurality of memory cells being connected with word lines and bit lines;
• a selection transistor which selects the word lines;
• and
• a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, read and erase operations of data with respect to the memory cells,
• wherein the selection transistor is formed on a well, and a first negative voltage is supplied to the well and a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line in an erase verify read operation.