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US 7,411,822 B2Granted
Nonvolatile memory cell arrangement
AssigneeInfineon Technologies AG
InventorsMichael Specht, Franz Hofmann, Ulrich Dorda, Johannes Kretz, Lars Dreeskornfeld
Life of this patent
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Abstract
Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.
Claims19
A memory, comprising:
- a multiplicity of nonvolatile memory cells, each nonvolatile memory cell being formed by a memory transistor configured so that electrical charge carriers are stored in nonvolatile fashion;
- the memory transistors are arranged in a matrix having a plurality of rows and columns;
- a first source/drain terminal of each memory transistor of a first column coupled to an electrically conductive conductor track in a first metallization plane;
- a first source/drain terminal of each memory transistor of a second column adjacent to the first column coupled to an electrically conductive conductor track in a second metallization plane;
- a first source/drain terminal of each memory transistor of a third column adjacent to the second column coupled to an electrically conductive conductor track in the first metallization plane;
- and
- a first source/drain terminal of each memory transistor of a fourth column adjacent to the third column coupled to an electrically conductive conductor track in the second metallization plane,
- wherein the second metallization plane is different than the first metallization plane, wherein a second source/drain terminal of each memory transistor is connected to a respective electrically conductive conductor track in a third metallization plane, the third metallization plane being different than the first metallization plane and different than the second metallization plane.
5 more elements
A nonvolatile memory cell arrangement, comprising:
- a multiplicity of nonvolatile memory cells, each nonvolatile memory cell being formed by a memory transistor configured so that electrical charge carriers are stored in nonvolatile fashion, and wherein the memory transistors are arranged in a matrix having a plurality of rows and columns;
- a first source/drain terminal of each memory transistor of a first column coupled to an electrically conductive conductor track in a first metallization plane;
- a first source/drain terminal of each memory transistor of a second column adjacent to the first column coupled to an electrically conductive conductor track in a second metallization plane;
- a first source/drain terminal of each memory transistor of a third column adjacent to the second column coupled to an electrically conductive conductor track in the first metallization plane;
- and
- a first source/drain terminal of each memory transistor of a fourth column adjacent to the third column coupled to an electrically conductive conductor track in the second metallization plane,
- wherein the first and second metallization planes are not the same,
- wherein the conductor tracks are arranged in the column direction alongside the source/drain terminals and have, alongside a portion of the source/drain terminals of the memory transistors of a column, a projection extending perpendicularly to the column direction as far as above the respective source/drain terminal, and wherein the conductor tracks are coupled to the respective source/drain terminal by means of a respective projection and by means of a contact hole respectively provided below the latter.
5 more elements
A memory comprising:
- a plurality of memory cell transistors arranged in a matrix having a plurality of rows and columns;
- a first source/drain terminal of each memory transistor of a first column coupled to an electrically conductive conductor track in a first metallization plane;
- a first source/drain terminal of each memory transistor of a second column adjacent to the first column coupled to an electrically conductive conductor track in a second metallization plane;
- a first source/drain terminal of each memory transistor of a third column adjacent to the second column coupled to an electrically conductive conductor track in the first metallization plane;
- and
- a first source/drain terminal of each memory transistor of a fourth column adjacent to the third column coupled to an electrically conductive conductor track in the second metallization plane,
- the second metallization plane being different than the first metallization plane, wherein second source/drain terminal of each memory transistor is connected to a respective electrically conductive conductor track in a third metallization plane, the third metallization plane being different than the first metallization plane and different than the second metallization plane.
4 more elements
Dependencies are inferred from the claim text.