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US 7,411,437 B2Granted
Triggering events at fractions of a clock cycle
AssigneeAgilent Technologies, Inc.
InventorsDietrich Werner Vook, Vamsi Krishna Srikantam, Andrew Fernandez
Life of this patent
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Abstract
Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or more delay circuits that trigger the event signal at a predetermined phase of the clock cycle by moving the event signal from a first clock domain to another clock domain. By triggering the event at a phase division, the triggering circuit outputs signals at a rate faster than the clock cycle.
Claims19
A triggering circuit, comprising:
- two or more input circuits, each input circuit arranged such that each input circuit receives an input signal and one of the input circuits receives a phase selection signal and outputs an event signal in response to receiving the input signal;
- and
- two or more delay circuits, wherein each delay circuit is in electrical communication with one of the input circuits, and wherein one delay circuit receives the event signal and is configured to trigger the event signal at a predetermined phase of a clock cycle, wherein the two or more delay circuits comprise one or more delay elements, and wherein at least one delay element triggers the event signal such that the event signal moves from one clock domain to another clock domain.
A triggering circuit, comprising:
- two or more input circuits, each input circuit arranged such that each input circuit receives an input signal and one of the input circuits receives a phase selection signal and outputs an event signal in response to receiving the input signal;
- and
- two or more delay circuits, wherein each delay circuit is in electrical communication with one of the input circuits, and wherein one delay circuit receives the event signal and is configured to trigger the event signal at a predetermined phase of a clock cycle;
- wherein at least one delay circuit, comprising two or more delay elements, moves the event signal from a first clock domain in which the event signal was generated to a second clock domain in which the event signal is output.
1 more element
A triggering circuit, comprising:
- two or more input circuits, each input circuit arranged such that each input circuit receives an input signal and one of the input circuits receives a phase selection signal and outputs an event signal in response to receiving the input signal;
- two or more delay circuits, wherein each delay circuit is in electrical communication with one of the input circuits, and wherein one delay circuit receives the event signal and is configured to trigger the event signal at a predetermined phase of a clock cycle, thereby moving the event signal from a first clock domain having a first phase in which the event signal was generated to a second clock domain having a second phase;
- and
- an output circuit in electrical communication with each delay circuit such that the output circuit receives the event signal output from one of the delay circuits and outputs the event signal;
- wherein the output circuit is an OR gate.
2 more elements
A triggering circuit, comprising:
- two or more input circuits, each input circuit arranged such that each input circuit receives an input signal and one of the input circuits receives a phase selection signal and outputs an event signal in response to receiving the input signal;
- and
- two or more delay circuits, wherein each delay circuit is in electrical communication with one of the input circuits, and wherein one delay circuit receives the event signal and is configured to trigger the event signal at a predetermined phase of a clock cycle, thereby moving the event signal from a first clock domain having a first phase in which the event signal was generated to a second clock domain having a second phase;
- wherein at least one input circuit is an AND gate.
1 more element
A method for triggering an event signal at a predetermined time, comprising:
- receiving an input signal at an input circuit;
- receiving a phase selection signal at the input circuit;
- generating an event signal, from the input circuit, in response to the phase selection signal and the input signal;
- receiving the event signal at a delay circuit, wherein the delay circuit comprises one or more delay elements;
- and
- triggering, by one of the delay elements, the event signal at a predetermined phase of a clock cycle, wherein the event signal moves from one clock domain to another clock domain.
3 more elements
Dependencies are inferred from the claim text.