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US 7,411,433 B2Granted
Reset ramp control
AssigneeSTMicroelectronics S.r.l.
InventorsDavid Charles McClure, Rong Yin
Life of this patent
Estimating the term…
Abstract
A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.
Claims26
A reset ramp control structure, comprising:
- a reset system element, coupled to the voltage to be monitored;
- and
- a fast ramp down detection element, which is coupled to the reset system element, and
- wherein during a ramp down condition of the voltage to be monitored the fast ramp down detection element forces an output of the reset system element to a known value and wherein during a slow ramp down condition of the voltage to be monitored the output of the reset system element is not forced by the fast ramp down detection element, and
- wherein the fast ramp down detection element further comprises:
- the voltage to be monitored is coupled to an anode of a diode;
- a first resistive element is coupled between a cathode of the diode and ground, and to an input terminal of an inverter;
- a gate of a transistor is coupled to an output of the inverter;
- a source of the transistor is coupled to ground;
- and
- a drain of the transistor is coupled to an output of the reset system element and to a capacitor.
8 more elements
A reset ramp control structure, comprising:
- a reset system element, coupled to the voltage to be monitored;
- and
- a fast ramp down detection element, which is coupled to the reset system element, and
- wherein during a ramp down condition of the voltage to be monitored the fast ramp down detection element forces an output of the reset system element to a known value and wherein during a slow ramp down condition of the voltage to be monitored the output of the reset system element is not forced by the fast ramp down detection element, wherein the fast ramp down detection element further comprises:
- the voltage to be monitored is coupled to a first conduction terminal of a first transistor;
- and
- a terminal of a first resistive element is coupled to a second conduction terminal of the first transistor and to an input terminal of an inverter, a control terminal of the first transistor coupled in a way to make the first transistor behave as a diode;
- and
- a gate of a second transistor is coupled to an output of the inverter;
- and
- the source of the second transistor is coupled to ground;
- and
- the drain of the second transistor is coupled to an output of the reset system element and to a capacitor.
10 more elements
A reset ramp control apparatus, operable to supply nonambiguous control of a system reset during fast ramp down conditions, comprising:
- a fast ramp down detection element to force an output of the system reset to a known state during a fast ramp down condition of a monitored voltage in accordance with a reset delay;
- and
- means to modify the reset delay,
- wherein during a slow ramp down condition of the voltage to be monitored the output of the system reset is not forced,
- wherein the fast ramp down detection element further comprises:
- the voltage to be monitored is coupled to an anode of a diode;
- a first resistive element is coupled between a cathode of the diode and ground, and to an input terminal of an inverter;
- a gate of a transistor is coupled to an output of the inverter;
- a source of the transistor is coupled to ground;
- and
- a drain of the transistor is coupled to an output of a reset element and to a capacitor.
8 more elements
A reset ramp control apparatus, operable to supply nonambigiuous control of a system reset during fast ramp down conditions, comprising:
- a fast ramp down detection element to force an output of the system reset to a known state during a fast ramp down condition of a monitored voltage in accordance with a reset delay;
- and
- means to modify the reset delay, wherein during a slow ramp down condition of the voltage to be monitored the output of the system reset is not forced, wherein the fast ramp down detection element further comprises:
- the voltage to be monitored is coupled to a source of a first transistor;
- and
- a first resistive element is coupled between a drain a gate of the first transistor and ground, and to an input terminal of an inverter;
- and
- a gate of a second transistor is coupled to an output of the inverter;
- and
- a source of the second transistor is coupled to ground;
- and
- a drain of the second transistor is coupled to an output of the reset system element and to a capacitor.
9 more elements
Dependencies are inferred from the claim text.