US 7,411,432 B1Granted

Integrated circuits and complementary CMOS circuits for frequency dividers

AssigneeLattice Semiconductor Corporation

InventorXiang Zhu

Life of this patent

Estimating the term…

Loading patent…

Abstract

An integrated circuit of an embodiment may comprise synchronous logic, combinational logic, and clock circuitry to clock the synchronous logic through various states dependent on the combinational logic. The synchronous logic may comprise a plurality of master-slave registers. The combinational logic is configured to drive data inputs of the synchronous logic dependent on states established by the master-slave registers. The clock circuitry is configured to clock the master portion of the master-slave registers with a lag rendering of a clock signal and to clock the slave portion of the registers with a lead rendering of the clock signal. In a particular example, the circuitry may define a frequency divider of a complementary CMOS realization.

Claims12

Dependent claims

An integrated circuit, comprising:

synchronous logic having at least one master-slave register with a data input, in which the master portion comprises a first latch and true and complementary gatable data paths driving the respective true and complementary nodes of the first latch, and the slave portion comprises a second latch and true and complementary gatable data paths to drive the respective true and complementary nodes of the second latch, the gatable data paths each comprising a switch configured to enable selective transfer of a signal therethrough dependent on a gate signal, and an inverter disposed electrically in series with the switch;
combinational logic to electrically drive at least one data input of the synchronous logic;
and
a clocking circuit to clock the master portion and the slave portion of the at least one master-slave register with respective lag and lead relative renderings of a clock signal, the clocking circuit configured to selectively enable the gatable data paths of the master portion based on the lag rendering of the clock signal and to selectively enable the gatable data paths of the slave portion based on the lead rendering of the clock signal, the clock circuit comprising:
a first latch of CMOS inverters inter-coupled input-to-output and output-to-input for the respective true and complementary nodes;
a second latch of CMOS inverters inter-coupled input-to-output and output-to-input for the respective true and complementary nodes;
a first inverter to invert and forward a signal from the true node of the first latch to a true node of the second latch;
and
a second inverter to invert and forward a signal from the complementary node of the first latch to a complementary node of the second latch;
the true and complementary nodes of the second latch of the clock circuit operable together as a differential output to source the lag rendering of the clock signal and to drive the switches in the data paths of the master portion of the master-slave register;
and
the true and complementary nodes of the first latch of the clock circuit operable together as a differential output to source the lead rendering of the clock signal and to drive the switches in the data paths of the slave portion of the master-slave register.

9 more elements

An integrated circuit, comprising:

synchronous logic having at least one master-slave register with a data input, wherein the master portion comprises a first latch and true and complementary gatable data paths driving the respective true and complementary nodes of the first latch, and the slave portion comprises a second latch and true and complementary gatable data paths to drive the respective true and complementary nodes of the second latch, the gatable data paths each comprising a switch configured to enable selective transfer of a signal therethrough dependent on a gate signal, and an inverter disposed electrically in series with the switch;
combinational logic to electrically drive at least one data input of the synchronous logic, the combinational logic operable to drive the true and complementary data paths of the master portion of the at least one master-slave register based on signal of the true and complementary nodes of the latch of the slave portion of the at least one master-slave register;
and
a clocking circuit to clock the master portion and the slave portion of the at least one master-slave register with respective lag and lead relative renderings of a clock signal, the clocking circuit configured to selectively enable the gatable data paths of the master portion based on the lag rendering of the clock signal and to selectively enable the gatable data paths of the slave portion based on the lead rendering of the clock signal,
wherein:
the synchronous logic comprises first, second and third ones of the master-slave register;
and
the combinational logic comprises:
first logic operable to differentially drive the true and complementary data paths of the master portion of the first master-slave register based on a first logic combination of signals of at least two of the true and complementary nodes of the respective latches of the slave portions of the first, the second and the third master-slave registers;
second logic operable to differentially drive the true and complementary data paths of the master portion of the second master-slave register based on a second logic combination of the signals of at least two of the true and complementary nodes of the respective latches of the slave portions of the first, the second and the third master-slave registers;
and
third logic operable to differentially drive the true and complementary data paths of the master portion of the third master-slave register based on a third logic combination of the signals of at least two of the true and complementary nodes of the respective latches of the slave portions of the first, the second and the third master-slave registers;
and the first, the second and the third logic are defined together with the first, the second and the third master-slave registers to form a frequency divider operable to divide the frequency of the clock signal.

10 more elements

Dependencies are inferred from the claim text.