US 7,411,427 B1Granted

Clock input filter circuit

AssigneeZilog, Inc.

InventorSteven K. Fong

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Abstract

A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Claims19

Dependent claims

A circuit comprising:

a first low-pass delay element that receives a first signal and outputs a first delayed version of the first signal;
a first logic gate that receives the first signal and the first delayed version of the first signal;
a second low-pass delay element that receives the first signal and outputs a second delayed version of the first signal;
a second logic gate that receives the first signal and the second delayed version of the first signal;
a sequential logic element that is set in response to a signal output by the first logic gate, and that is reset in response to a signal output by the second logic gate;
a third logic gate that has a first input lead and a second input lead, the first signal being present on the first input lead, the second input lead being coupled to receive a signal output by the sequential logic element;
a fourth logic gate that has a first input lead and a second input lead, the first signal lead being present on the first input lead, the second input lead being coupled to receive the signal output by the sequential logic element;
and
multiplexing circuitry that has a first input lead, a second input lead, a third input lead, and an output lead, wherein the first input lead is coupled to receive a signal output by the third logic gate, wherein the second input lead is coupled to receive the signal output by the sequential logic element, and wherein the third input lead is coupled to receive a signal output by the fourth logic gate.

6 more elements

An integrated circuit comprising:

a processor;
a first gate having a first input lead, a second input lead, and an output lead;
a first logic element having an input lead and an output lead, the input lead of the first logic element being coupled to the first input lead of the first gate;
a first RC network having an input lead and an output lead, wherein the first RC network has a first processor-programmable RC time constant, and wherein the input lead of the first RC network is coupled to the output lead of the first logic element;
a first hysteresis logic element having an input lead and an output lead, wherein the input lead of the first hysteresis logic element is coupled to the output lead of the first RC network, and wherein the output lead of the first hysteresis logic element is coupled to the second input lead of the first gate;
a first transistor having a drain, a source and a gate, wherein the drain is coupled to the input lead of the hysteresis logic element, wherein the source is coupled to a supply voltage conductor, and wherein the gate is coupled to the first input lead of the first gate;
a latch having a first input lead, a second input lead, and an output lead, wherein the first input lead of the latch is coupled to receive a signal output from the first gate;
a second gate having a first input lead, a second input lead, and an output lead, wherein the first input lead of the second gate is coupled to the first input lead of the first gate, wherein the output lead of the second gate is coupled to supply a signal output by the second gate onto the second input lead of the latch;
a second logic element having an input lead and an output lead, the input lead of the second logic element being coupled to the first input lead of the second gate;
a second RC network having an input lead and an output lead, wherein the second RC network has a second processor-programmable RC time constant, and wherein the input lead of the second RC network is coupled to the output lead of the second logic element;
a second hysteresis logic element having an input lead and an output lead, wherein the input lead of the second hysteresis logic element is coupled to the output lead of the second RC network, and wherein the output lead of the second hysteresis logic element is coupled to the second input lead of the second gate;
and
a second transistor having a drain, a source and a gate, wherein the drain is coupled to the input lead of the second hysteresis logic element, wherein the source is coupled to a ground conductor, and wherein the gate is coupled to the first input lead of the second gate.

10 more elements

Dependencies are inferred from the claim text.