US 7,411,411 B1 · Methods and systems for hardening a clocked latch against single event effects

Abstract

Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a second NAND gate. The first three-input OR gate receives as inputs a clock signal, a first signal, and a redundant first signal. An output of the first three-input OR gate is connected to an input of the first NAND gate. The second three-input OR gate receives as inputs the clock signal, a second signal, and a redundant second signal. An output of the second three-input OR gate is connected to an input of the second NAND gate. A first output signal of the first NAND gate is connected to another input of the second NAND gate and a second output signal of the second NAND gate is connected to another input of the first NAND gate.

Claims20

Dependent claims

A system for hardening a clocked latch against single event effects, the system comprising:

a first three-input OR gate;
a first NAND gate that (i) includes a first input and second input and (ii) produces a first output signal;
a second three-input OR gate;
and
a second NAND gate that (i) includes a third input and fourth input and (ii) produces a second output signal,
wherein the first three-input OR gate receives as inputs a clock signal, a first signal, and a redundant first signal, and wherein an output of the first three-input OR gate is connected to the first input of the first NAND gate,
wherein the second three-input OR gate receives as inputs the clock signal, a second signal, and a redundant second signal, and wherein an output of the second three-input OR gate is connected to the third input of the second NAND gate, and
wherein the first output signal is connected to the fourth input of the second NAND gate, and wherein the second output signal is connected to the second input of the first NAND gate.

5 more elements

A method for operating a clocked latch that is hardened against single event effects, the method comprising:

providing a first signal, redundant first signal, and clock signal to a first three-input OR gate;
providing an output of the first three-input OR gate to a first input of a first NAND gate;
providing a second signal, redundant second signal, and the clock signal to a second three-input OR gate;
providing an output of the second three-input OR gate to a first input of a second NAND gate;
providing an output signal of the first NAND gate to a second input of the second NAND gate;
and
providing an output signal of the second NAND gate to a second input of the first NAND gate.

4 more elements

Dependencies are inferred from the claim text.

Methods and systems for hardening a clocked latch against single event effects

Life of this patent

Methods and systems for hardening a clocked latch against single event effects

Life of this patent

Abstract

Claims20