Self-aligned, low-resistance, efficient memory array
AssigneeMicron Technology, Inc.
InventorJames G. Deak
Life of this patent
Estimating the term…
Abstract
The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.
Claims12
A memory array structure, comprising:
- a plurality of memory cell structures, each of said memory cell structures comprising:
- a trench in a first insulating layer defining first and second levels, said and second levels being connected by at least a sidewall region;
- a ferromagnetic cladding layer formed within said trench and over said second level and said sidewall region of said first insulating layer;
- a first conductive layer formed within said trench and over a second level and a sidewall region of said ferromagnetic cladding layer;
- a second insulating layer formed within said trench and over a second level and a sidewall region of said first conductive layer;
- a second conductive layer formed within said trench;
- and
- a magnetic tunnel junction element formed over said second conductive layer.
A memory device comprising a plurality of magnetoresistive random access memory cell structures arranged in an array, each of said magnetoresistive random access memory cell structures comprising:
- a trench in a first insulating layer defining first and second levels, said and second levels being connected by at least a sidewall region;
- a ferromagnetic cladding layer formed within said trench and over said second level and said sidewall region of said first insulating layer;
- a first conductive layer formed within said trench and over a second level and a sidewall region of said ferromagnetic cladding layer;
- a second insulating layer formed within said trench and over a second level and a sidewall region of said first conductive layer;
- a second conductive layer formed within said trench;
- and
- a magnetic tunnel junction element formed over said second conductive layer.
A memory cell array comprising:
- a plurality of magnetoresistive random access memory cell structures, each of said magnetoresistive random access memory cell structures comprising:
- a trench in a first insulating layer defining first and second levels, said and second levels being connected by at least a sidewall region;
- a ferromagnetic cladding layer formed within said trench and over said second level and said sidewall region of said first insulating layer;
- a first conductive layer formed within said trench and over a second level and a sidewall region of said ferromagnetic cladding layer;
- a second insulating layer formed within said trench and over a second level and a sidewall region of said first conductive layer;
- a second conductive layer formed within said trench;
- and
- a magnetic tunnel junction element formed over said second conductive layer.
Dependencies are inferred from the claim text.