US 7,411,255 B2 · Dopant barrier for doped glass in memory devices · patentgrep

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Abstract

A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

Claims52

Dependent claims

A semiconductor device comprising:

a substrate;
a plurality of diffusion regions formed in the substrate, the plurality of diffusion regions includes a first diffusion region, a second diffusion region, and a third diffusion region;
a plurality of gate structures formed over the substrate, the plurality of gate structures includes a first gate structure formed over a channel region between the first and second diffusion regions, and a second gate structure formed over a channel region between the second and third diffusion regions, wherein the first gate structure and the first and second diffusion regions form at least a portion of a first memory cell with the first diffusion region formed at least a portion of a storage node of the first memory cell, and wherein the second gate structure and the second and third diffusion regions form at least a portion of a second memory cell;
a diffusion barrier including an alumina layer formed on the gate structures, wherein the alumina layer remains in the semiconductor device after the semiconductor device is formed, wherein a first portion of the alumina layer completely covers a top surface of the first gate structure and completely covers a top surface of the second gate structure, wherein a second portion of the alumina layer is below the top surface of at least one of the first and second gate structures, wherein the diffusion barrier layer includes a first insulating layer and a second insulating layer, wherein the alumina layer is between the first and second insulating layers, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second gate structures, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second gate structures;
and
a doped glass layer formed on the diffusion barrier.

3 more elements

A semiconductor device comprising:

a first diffusion region formed in a substrate;
a second diffusion region formed in the substrate, the first and second diffusion regions being separated by a first channel region of the substrate;
a first gate structure formed over the first channel region;
a third diffusion region formed in the substrate, the third and second diffusion regions being separated by a second channel region of the substrate;
a second gate structure formed over the second channel region, wherein the first gate structure and the first and second diffusion regions form at least a portion of a first memory cell with the first diffusion region formed at least a portion of a storage node of the first memory cell, and wherein the second gate structure and the second and third diffusion regions form at least a portion of a second memory cell with the third diffusion region formed at least a portion of a storage node of the second memory cell;
an alumina layer formed over the first and second gate structures, wherein the alumina layer remains in the semiconductor device after the semiconductor device is formed, wherein a first potion of the alumina layer completely covers a top surface of the first gate structure and completely covers a top surface of the second gate structure, wherein a second portion of the alumina layer directly contacts at least one of the first and second gate structures;
and
a first insulating layer and a second insulating layer sandwiching the alumina layer, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second gate structures, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second gate structures.

5 more elements

A semiconductor device comprising:

a substrate;
a first diffusion region formed in the substrate;
a second diffusion region formed in the substrate, wherein the first and second diffusion regions are separated by a first channel region;
a first gate dielectric layer formed over the first channel region;
a first conductive layer formed over the first gate dielectric layer;
a third diffusion region formed in the substrate, wherein the third and second diffusion regions are separated by a second channel region;
a second gate dielectric layer formed over the second channel region;
a second conductive layer formed over the second gate dielectric layer;
an alumina layer formed over the first and second conductive layers, wherein the alumina layer remains in the semiconductor device after the semiconductor device is formed, wherein a first portion of the alumina layer completely covers a top surface of the first conductive layer and completely covers a top surface of the second conductive layer, and wherein a second portion of the alumina layer is below the top surface of at least one of the first and second conductive layers;
a first insulating layer and a second insulating layer sandwiching the alumina layer, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second conductive layers, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second conductive layers;
and
a first conductive contact structure coupled to the first diffusion region to provide electrical connection to the first diffusion region.

9 more elements

A semiconductor device comprising:

a first diffusion region formed in a substrate;
a second diffusion region formed in the substrate, the first and second diffusion regions being separated by a first channel region of the substrate;
a first word line formed over the first channel region;
a third diffusion region formed in the substrate, the third and second diffusion regions being separated by a second channel region of the substrate;
a second word line formed over the second channel region, wherein the first word line and the first and second diffusion regions form at least a portion of a first memory cell, and wherein the second word line and the second and third diffusion regions form at least a portion of a second memory cell;
a diffusion barrier formed over the first and second word lines, the diffusion barrier including an alumina layer, wherein the alumina layer remains in the semiconductor device after the semiconductor device is formed, wherein a first portion of the alumina layer completely covers a top surface of the first word line and completely covers a top surface of the second word line, wherein a second portion of the alumina layer is below the top surface of at least one of the first and second word lines, wherein the diffusion barrier layer includes a first insulating layer and a second insulating layer, wherein the alumina layer is between the first and second insulating layers, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second word lines, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second word lines;
a first conductive contact structure coupled to the first diffusion region to provide electrical connection to the first diffusion region;
and
a second conductive contact structure coupled to the second diffusion region to provide electrical connection to the second diffusion region.

6 more elements

A semiconductor device comprising:

a first diffusion region formed in a substrate;
a second diffusion region formed in the substrate, the first and second diffusion regions being separated by a first channel region of the substrate;
a first gate structure formed over the first channel region;
a third diffusion region formed in the substrate, the third and second diffusion regions being separated by a second channel region of the substrate;
a second gate structure formed over the second channel region, wherein the first gate structure and the first and second diffusion regions form at least a portion of a first memory cell with the first diffusion region formed at least a portion of a storage node of the first memory cell, and wherein the second gate structure and the second and third diffusion regions form at least a portion of a second memory cell;
a dielectric layer formed over the first and second gate structures and the substrate;
a diffusion barrier for preventing diffusion between the dielectric layer and the first and second gate structures and for preventing diffusion between the dielectric layer and the substrate, the diffusion barrier including an alumina layer, wherein the alumina layer remains in the semiconductor device after the semiconductor device is formed, wherein the alumina layer completely covers a top surface of the first gate structure and completely covers a top surface of the second gate structure, wherein the diffusion barrier layer includes a first insulating layer and a second insulating layer, wherein the alumina layer is between the first and second insulating layers, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second gate structures, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second gate structures;
a first conductive contact structure coupled to the first diffusion region to provide electrical connection to the first diffusion region;
and
a second conductive contact structure coupled to the second diffusion region to provide electrical connection to the second diffusion region.

7 more elements

A memory device comprising:

a plurality of memory cells arrange in rows and columns;
a row decoder coupled to the memory cells;
and
a column decoder coupled to the memory cells, wherein the memory cells include:
a first diffusion region formed in a substrate;
a second diffusion region formed in the substrate, the first and second diffusion regions being separated by a first channel region of the substrate;
a first gate structure formed over the first channel region;
a third diffusion region formed in the substrate, the third and second diffusion regions being separated by a second channel region of the substrate;
a second gate structure formed over the second channel region, wherein the first gate structure and the first and second diffusion regions form at least a portion of a first memory cell of the plurality of memory cells with the first diffusion region formed at least a portion of a capacitor of the first memory cell, wherein a first potion of the second gate structure and the second and third diffusion regions form at least a portion of a second memory cell of the plurality of memory cells;
and
an alumina layer formed over the gate structure, wherein the alumina layer remains in the semiconductor device after the memory device is formed, wherein a first portion of the alumina layer completely covers a top surface of the first gate structure and completely covers a top surface of the second gate structure, and wherein a second portion of the alumina layer is below the top surface of at least one of the first and second gate structures;
and
a first insulating layer and a second insulating layer sandwiching the alumina layer, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second gate structures, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second gate structures.

10 more elements

A system comprising:

a processor;
and
a semiconductor device connected to the processor, the semiconductor device including a plurality of memory cells, the memory cells including:
a first diffusion region formed in a substrate;
a second diffusion region formed in the substrate, the first and second diffusion regions being separated by a first channel region of the substrate;
a first gate structure formed over the first channel region;
a third diffusion region formed in the substrate, the third and second diffusion regions being separated by a second channel region of the substrate;
a second gate structure formed over the second channel region, wherein the first gate structure and the first and second diffusion regions form at least a portion of a first memory cell of the plurality of memory cells with the first diffusion region formed at least a portion of a capacitor of the first memory cell, and wherein the second gate structure and the second and third diffusion regions form at least a portion of a second memory cell of the plurality of memory cells;
and
an alumina layer formed over the gate structure, wherein the alumina layer remains in the semiconductor device after the memory device is formed, wherein a first portion of the alumina layer completely covers a top surface of the first gate structure and completely covers a top surface of the second gate structure, wherein a second portion of the alumina layer is below the top surface of at least one of the first and second gate structures;
and
a first insulating layer and a second insulating layer sandwiching the alumina layer, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second gate structures, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second gate structures.

9 more elements

A system comprising:

a processor;
and
a memory device connected to the processor, the memory device including:
a substrate;
a plurality of diffusion regions formed in the substrate, the plurality of diffusion regions includes a first diffusion region, a second diffusion region, and a third diffusion region;
a plurality of gate structures formed over the substrate, the plurality of gate structures includes a first gate structure formed over a channel region between the first and second diffusion regions, and a second gate structure formed over a channel region between the second and third diffusion regions, wherein the first gate structure and the first and second diffusion regions form at least a portion of a first memory cell of the memory device with the first diffusion region formed at least a portion of a capacitor of the first memory cell, and wherein the second gate structure and the second and third diffusion regions form at least a portion of a second memory cell of the memory device with the third diffusion region formed at least a portion of a capacitor of the second memory cell;
a diffusion barrier including an alumina layer formed on the gate structures, wherein the alumina layer remains in the memory device after the memory device is formed, wherein a first portion of the alumina layer completely covers a top surface of the first gate structure and completely covers a top surface of the second gate structure, wherein a second portion of the alumina layer is below the top surface of at least one of the first and second gate structures, wherein the diffusion barrier layer includes a first insulating layer and a second insulating layer, wherein the alumina layer is between the first and second insulating layers, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second gate structures, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second gate structures;
and
a glass layer formed on the diffusion barrier.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/003,138Filed 3 Dec 2004 · division
Priority: 29 Aug 2002
Published: US 2005/0151179 A114 Jul 2005
Granted: 12 Aug 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10D 64/01354
The insulator being formed after the semiconductor body, the semiconductor being silicon: passivation or protection of the electrode, e.g. using…
H10P 95/94
Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass: hydrogenation or deuterisation,…
H10W 20/075
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: of multilayered…

Family

Application10/233,279Parent of this division · filed 29 Aug 2002
US 2005/0151179 A1Pre-grant publication · published 14 Jul 2005
US 6,833,575 B2Parent of this division
US 2004/0043566 A1Published application
US 7,411,255 B2This patent

From the US filing history. Foreign family members aren’t listed.

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