Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby

An electrically programmable and erasable memory device comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
• an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
• an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• and
• a trench formed into the substrate surface, wherein the second region is formed underneath the trench, and wherein the channel region first portion extends substantially along a sidewall of the trench and the channel region second portion extends substantially along the surface of the substrate;
• wherein each of the floating gate first and second elongated portions has a distal end that terminates in a thin tip portion the directly faces and is insulated from the control gate.

An electrically programmable and erasable memory device comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
• an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
• an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• and
• a trench formed into the substrate surface, wherein the first region is formed underneath the trench, and wherein the channel region second portion extends substantially along a sidewall of the trench and the channel region first portion extends substantially along the surface of the substrate;
• wherein each of the floating gate first and second elongated portions has a distal end that terminates in a thin tip portion the directly faces and is insulated from the control gate.

An electrically programmable and erasable memory device comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
• an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
• an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• and
• a trench formed into the substrate surface, wherein the first region is formed underneath the trench, and wherein the channel region second portion extends substantially along a sidewall of the trench and the channel region first portion extends substantially along the surface of the substrate;
• wherein the floating gate second portion extends over and is insulated from a bottom surface of the trench, and wherein the floating gate first portion extends along and is insulated from the sidewall of the trench.

An electrically programmable and erasable memory device comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
• an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
• an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• a trench formed into the substrate surface, wherein the first region is formed underneath the trench, and wherein the channel region second portion extends substantially along a sidewall of the trench and the channel region first portion extends substantially along the surface of the substrate;
• and
• a block of conductive material having at least a lower portion thereof disposed in the trench laterally adjacent to and insulated from the floating gate.

An array of electrically programmable and erasable memory devices comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• each of the active regions including a plurality of memory cells, each of the memory cells comprising:
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having first and second portions,
• an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region, and
• an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• wherein each of the floating gate first and second elongated portions has a distal end that terminates in a thin tip portion the directly faces and is insulated from the control gate;
• wherein each of the floating gate second portions extends in a direction substantially perpendicular to the substrate surface.

An array of electrically programmable and erasable memory devices comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• each of the active regions including a plurality of memory cells, each of the memory cells comprising:
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having first and second portions,
• an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region, and
• an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• and
• a plurality of trenches formed into the substrate surface which are substantially parallel to one another and extend in a second direction substantially perpendicular to the first direction, wherein each of the second regions is formed underneath one of the trenches, and wherein each of the channel region first portions extends substantially along a sidewall of one of the trenches and each of the channel region second portions extends substantially along the surface of the substrate.

An array of electrically programmable and erasable memory devices comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• each of the active regions including a plurality of memory cells, each of the memory cells comprising:
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having first and second portions,
• an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region, and
• an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• and
• a plurality of trenches formed into the substrate surface which are substantially parallel to one another and extend in a second direction substantially perpendicular to the first direction, wherein each of the first regions is formed underneath one of the trenches, and wherein each of the channel region second portions extends substantially along a sidewall of one of the trenches and each of the channel region first portions extends substantially along the surface of the substrate.