High performance FET devices and methods thereof
AssigneeInternational Business Machines Corporation
InventorJack Oon Chu
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Abstract
Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.
Claims8
A multifaceted gate MOSFET device on insulator, comprising:
- a strained monocrystalline Si based strip, wherein the Si based strip has a Ge content of between about 70% and about 95%, the Si based strip comprising a middle section and two end sections, the middle section comprising a multifaceted channel region, wherein the end sections comprise a source and a drain;
- a gate insulator covering the channel region;
- a gate overlaying at least two facets of the multifaceted channel region, and interfacing with the gate insulator;
- and
- a supporting platform bonding the Si based strip.
Dependencies are inferred from the claim text.