US 7,410,913 B2Granted

Method of manufacturing silicon rich oxide (SRO) and semiconductor device employing SRO

AssigneeSamsung Electronics Co., Ltd.

InventorsJung-Hyun Lee, Sang-Bong Bang

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Abstract

Provided are methods for manufacturing silicon rich oxide (SRO) layers useful in the fabrication of semiconductor devices, for example, non-volatile memory devices, and methods for fabricating semiconductor devices incorporating such SRO layers. The methods include absorbing a first silicon source gas onto the substrate, oxidizing the first absorbed layer to form a silicon oxide layer, absorbing a second silicon source gas onto the substrate and reducing the second absorbed layer to form a silicon layer. The combination of the silicon oxide layer(s) and the silicon layer(s) comprise, in turn, a composite SRO layer. These manufacturing methods facilitate control of the oxygen concentration in the SRO, the relative thicknesses of the silicon oxide and silicon layers, and provides improved step coverage, thus allowing the manufacturing of high quality semiconductor devices.

Claims31

Dependent claims

A method of forming a silicon rich oxide (SRO) layer on a substrate comprising:

a) introducing the substrate into a reaction chamber;
b) introducing a first silicon source gas into the reaction chamber under conditions whereby a portion of the first silicon source gas is absorbed on a first substrate surface to form a first silicon source layer, the first silicon source gas being substantially free of oxygen;
c) introducing a first reaction gas into the reaction chamber under conditions sufficient to form an oxidizing plasma;
d) reacting the first silicon source layer and the oxidizing plasma to form a silicon oxide layer on the first substrate surface;
e) introducing a second silicon source gas into the reaction chamber under conditions whereby a portion of the second silicon source gas is absorbed on a surface of the silicon oxide layer to form a second silicon source layer, the second silicon source gas being substantially free of oxygen;
f) introducing a second reaction gas into the reaction chamber under conditions sufficient to form a reducing plasma;
and
g) reacting the second silicon source layer and the reducing plasma to form a silicon layer, wherein the combination of the silicon oxide layer and the silicon layer comprise the SRO layer.

5 more elements

A method of manufacturing a semiconductor device comprising:

forming an active region on a semiconductor substrate;
forming a gate insulating layer on the active region;
and
forming a gate electrode on the gate insulating layer for controlling an electrical field within the portion of the active layer underlying the gate electrode,
wherein forming the gate insulating layer further comprises fabricating a silicon rich oxide (SRO) layer by
a) absorbing a first silicon source gas onto a substrate surface to form a first silicon source layer, the first silicon source gas being substantially free of oxygen;
b) oxidizing the first silicon source layer to form a silicon oxide layer;
c) absorbing a second silicon source gas onto a substrate surface to form a second silicon source layer, the second silicon source gas being substantially free of oxygen;
and
d) reducing the second silicon source layer to form a silicon layer;
wherein the silicon oxide layer and the silicon layer comprise the SRO layer.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/519,083Filed 12 Sep 2006
Published: US 2007/0072424 A129 Mar 2007
Granted: 12 Aug 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

C23C 16/401
Oxides: containing silicon
C23C 16/45525
Pulsed gas flow or change of composition over time: atomic layer deposition [ALD]
C23C 16/45529
Characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures…
H10P 14/416
Of conductive or resistive materials: of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers

Family

US 2007/0072424 A1Pre-grant publication · published 29 Mar 2007
US 7,410,913 B2This patent

From the US filing history. Foreign family members aren’t listed.

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