Semiconductor structure and fabrication thereof
AssigneeUnited Microelectronics Corp.
InventorsShyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Tzyy-Ming Cheng
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Abstract
A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.
Claims21
A method for fabricating a semiconductor structure, comprising:
- providing a substrate having thereon a gate structure and a spacer on a sidewall of the gate structure and having therein an S/D extension region beside the gate structure;
- forming an opening in the substrate beside the spacer;
- forming an S/D region in or on the substrate at bottom of the opening;
- forming a metal silicide layer on the S/D region and the gate structure;
- and
- forming a stress layer over the substrate and filling the opening, wherein the stress layer has a sufficient thickness to at least fill up the opening.
A method for fabricating a semiconductor structure, comprising:
- providing a substrate having a first and a second gate structures thereon;
- forming a first S/D extension region of a first conductivity type in the substrate beside the first gate structure, and forming a second S/D extension region of a second conductivity type in the substrate beside the second gate structure;
- forming a first spacer on a sidewall of the first gate structure, and forming a second spacer on a sidewall of the second gate structure;
- forming an opening in the substrate beside the first spacer;
- forming a first S/D region of the first conductivity type in or on the substrate at bottom of the opening to form a first MOS transistor of the first conductivity type, and forming a second S/D region of the second conductivity type in the substrate beside the second spacer to form a second MOS transistor of the second conductivity type;
- and
- forming a first stress layer over the first MOS transistor and filling the opening, and forming a second stress layer over the second MOS transistor, wherein the first stress layer has a sufficient thickness to at least fill up the opening.
Dependencies are inferred from the claim text.