Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure

A method for making an integrated circuit comprising:

• forming at least one first conductive layer adjacent a first portion of a semiconductor substrate;
• forming a second conductive layer adjacent a second portion of the semiconductor substrate;
• forming a plurality of memory cells in the at least one first conductive layer and the first portion of the semiconductor substrate;
• forming a first sealing layer on the plurality of memory cells including sidewalls thereof;
• forming protective spacers on the first sealing layer for the plurality of memory cells, each protective spacer comprising a protective layer;
• forming a plurality of transistors in the second conductive layer;
• and
• forming a second sealing layer on the plurality of transistors including sidewalls thereof, and directly on the first sealing layer.

An integrated circuit comprising:

• a semiconductor substrate including first and second portions;
• a plurality of first electronic devices adjacent the first portion of said semiconductor substrate, each first electronic device including a first region comprising at least one first conductive layer projecting from said semiconductor substrate;
• a first sealing layer on said plurality of first electronic devices including sidewalls thereof;
• protective spacers on said first sealing layer for said plurality of first electronic devices, each protective spacer comprising a protective layer;
• a plurality of second electronic devices adjacent the second portion of said semiconductor substrate, each second electronic device including a second region comprising a second conductive layer projecting from said semiconductor substrate;
• and
• a second sealing layer on said plurality of second electronic devices including sidewalls thereof, and on portions of said first sealing layer and on said protective spacers for said plurality of first electronic devices, said second sealing layer covering top portions of said second regions of said plurality of second electronic devices, with said first sealing layer between the top portions and said second sealing layer.

An integrated circuit comprising:

• a semiconductor substrate including first and second portions;
• a plurality of memory cells adjacent the first portion of said semiconductor substrate;
• a first sealing layer on said plurality of memory cells including sidewalls thereof;
• protective spacers on said first sealing layer for the plurality of memory cells, each protective spacer comprising a protective layer;
• a plurality of transistors adjacent the second portion of said semiconductor substrate;
• and
• a second sealing layer on said plurality of transistors including sidewalls thereof and directly on said first sealing layer.

An integrated circuit comprising:

• a semiconductor substrate including first and second portions;
• a plurality of first electronic devices adjacent the first portion of said semiconductor substrate, each first electronic device including a first region comprising at least one first conductive layer projecting from said semiconductor substrate;
• first spacers on sidewalls of the first regions of said plurality of first electronic devices, said first spacers defined by a first sealing layer, a protective layer on said first sealing layer and a second sealing layer on said protective layer;
• a plurality of second electronic devices adjacent the second portion of said semiconductor substrate, each second electronic device including a second region comprising a second conductive layer projecting from said semiconductor substrate;
• and
• second spacers on sidewalls of the second regions of said plurality of second electronic devices, said second spacers defined by other portions of the second sealing layer,
• said second sealing layer covering top portions of said second regions of said plurality of second electronic devices, with said first sealing layer between the top portions and said second sealing layer.