Method of manufacturing lateral MOSFET structure of an integrated circuit having separated device regions
AssigneeIntersil Americas Inc.
InventorJames D. Beasom
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntersil Americas Inc.
InventorJames D. Beasom
Estimating the term…
Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.
A method of forming a pn junction diode in an integrated circuit, the method comprising:
Dependencies are inferred from the claim text.