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US 7,410,813 B1Granted
Method of parallel lapping a semiconductor die
AssigneeNational Semiconductor Corporation
InventorGengying Gao
Life of this patent
Estimating the term…
Abstract
In a lapping process for lapping away layers from a semiconductor device, where the region of interest is located near an edge or corner of the device, the method includes adding additional semiconductor material adjacent the region of interest.
Claims12
A method of performing fault analysis in a semiconductor die comprising,
- Locating a defect in an x-y plane of the semiconductor die,
- securing one or more pieces of additional semiconductor material adjacent the defect, wherein the size and location of the one or more pieces of additional semiconductor material are chosen so that the defect is located substantially near the center of the combined surface area of the semiconductor material of the die and the one or more pieces of additional semiconductor material, and
- lapping the semiconductor die to remove die material in a z-direction for analysis of the defect.
Dependencies are inferred from the claim text.