Use of a dual-tone resist to form photomasks including alignment mark protection, intermediate semiconductor device structures and bulk semiconductor device substrates

An intermediate semiconductor device structure, comprising:

• a fabrication substrate comprising at least one alignment mark;
• at least one material layer over the fabrication substrate;
• and
• a photomask over the at least one material layer, comprising:
• apertures located over at least a portion of the photomask, wherein the apertures are configured to facilitate etching of the at least one material layer on the fabrication substrate;
• and
• at least one alignment mark mask element formed of material of the photomask and positioned to substantially shield the at least one alignment mark without shielding portions of the at least one material layer adjacent to the at least one alignment mark, wherein at least one of the apertures extends to a peripheral edge of the at least one alignment mark mask element.

A semiconductor device structure, comprising:

• a fabrication substrate comprising at least one alignment mark on a peripheral edge thereof;
• at least one alignment mark mask clement comprising a photoresist material;
• and
• at least one semiconductor device feature on the fabrication substrate, wherein the at least one semiconductor device feature abuts a peripheral edge of the at least one alignment mark, and wherein the at least one alignment mark mask element substantially shields the at least one alignment mark without shielding portions of the at least one semiconductor device feature abutting the peripheral edge of the at least one alignment mark.

A semiconductor device structure, comprising:

• a bulk substrate fully populated with semiconductor die locations;
• at least one alignment mark mask element comprising a photoresist material;
• and
• at least one alignment mark located on a peripheral edge of the bulk substrate and residing within one of the semiconductor die locations, wherein the at least one alignment mark mask element substantially shields the at least one alignment mark without shielding portions of the semiconductor die locations adjacent to the at least one alignment mark.