Semiconductor device and method for manufacturing the same
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsHisao Ichijo, Hiroyoshi Ogura, Yoshinobu Sato, Teruhisa Ikuta
Life of this patent
Estimating the term…
Loading patent…
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsHisao Ichijo, Hiroyoshi Ogura, Yoshinobu Sato, Teruhisa Ikuta
Estimating the term…
An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate; a semiconductor layer having a P− type active region that is formed on the supporting substrate, interposing a buried oxide film between the semiconductor layer and the supporting substrate; and a gate electrode that is formed on the semiconductor layer, interposing a gate oxide film and a part of a LOCOS film between the gate electrode and the semiconductor layer, wherein the P− type active region has: an N+ type source region; a P type body region; a P+ type back gate contact region; an N type drain offset region; an N+ type drain contact region; and an N type drain buffer region that is formed in a limited region between the N type drain offset region and the P type body region, and the N type drain buffer region is in contact with a source side end of the LOCOS film and is shallower than the N type drain offset region.
A semiconductor device that is a MOS transistor, said semiconductor device comprising:
A semiconductor device that is a MOS transistor, said semiconductor device comprising:
Dependencies are inferred from the claim text.