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US 7,408,226 B2Granted
Electronic card with protection against aerial discharge
AssigneeKabushiki Kaisha Toshiba
InventorMakoto Takizawa
Life of this patent
Estimating the term…
Abstract
An electronic card includes a card terminal which is exposed on a surface of a card, a semiconductor integrated circuit chip including an insulated-gate field effect transistor, and a protection circuit which is provided between the card terminal and the insulated-gate field effect transistor. The protection circuit is configured to protect the insulated-gate field effect transistor from destruction against a pulse having a pulse width of 1 ns or less applied to the card terminal.
Claims17
A semiconductor integrated circuit device comprising:
- a semiconductor region of a first conductivity type;
- a first insulated-gate field effect transistor formed on the semiconductor region of the first conductivity type and having a drain region of a second conductivity type connected to an output terminal;
- a second insulated-gate field effect transistor formed on the semiconductor region of the first conductivity type and having a drain region of the second conductivity type connected to a gate of the first insulated-gate field effect transistor to drive the first insulated-gate field effect transistor;
- and
- a third insulated-gate field effect transistor formed on the semiconductor region of the first conductivity type and having a source region connected to a gate thereof and a drain region connected to the gate of the first insulated-gate field effect transistor, a distance from the drain region of the first insulated-gate field effect transistor to the drain region of the third insulated-gate field effect transistor which is connected to the gate of the first insulated-gate field effect transistor being shorter than a distance from the drain region of the first insulated-gate field effect transistor to the drain region of the second insulated-gate field effect transistor, the third insulated-gate field effect transistor being formed in an active region in which the first insulated-gate field effect transistor is formed,
- wherein the source region of the third insulated-gate field effect transistor is shared with the source region of the first insulated-gate field effect transistor.
3 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor region of a first conductivity type;
- a first insulated-gate field effect transistor formed on the semiconductor region of the first conductivity type and having a drain region of a second conductivity type connected to an output terminal;
- a second insulated-gate field effect transistor formed on the semiconductor region of the first conductivity type and having a drain region of the second conductivity type connected to a gate of the first insulated-gate field effect transistor to drive the first insulated-gate field effect transistor;
- and
- a third insulated-gate field effect transistor formed on the semiconductor region of the first conductivity type and having a source region connected to a gate thereof and a drain region connected to the gate of the first insulated-gate field effect transistor, a distance from the drain region of the first insulated-gate field effect transistor to the drain region of the third insulated-gate field effect transistor which is connected to the gate of the first insulated-gate field effect transistor being shorter than a distance from the drain region of the first insulated-gate field effect transistor to the drain region of the second insulated-gate field effect transistor, the third insulated-gate field effect transistor being formed in an active region in which the first insulated-gate field effect transistor is formed;
- a fourth insulated-gate field effect transistor formed on the semiconductor region of the first conductivity type and having a source region connected to a gate thereof and a drain region connected to the gate of the first insulated-gate field effect transistor,
- wherein a distance from the drain region of the first insulated-gate field effect transistor to the drain region of the fourth insulated-gate field effect transistor which is connected to the gate of the first insulated-gate field effect transistor is shorter than the distance from the drain region of the first insulated-gate field effect transistor to the drain region of the second insulated-gate field effect transistor, and
- the fourth insulated-gate field effect transistor is formed in the active region in which the first insulated-gate field effect transistor is formed, and
- the third and fourth insulated-gate field effect transistor are arranged in an arrayed shape along the gate length direction.
6 more elements
Dependencies are inferred from the claim text.