Vertical transistor structure for use in semiconductor device and method of forming the same

A structure comprising:

• a shallow trench insulator disposed in a semiconductor substrate to define an active region and a non-active region of the semiconductor substrate;
• gate electrodes disposed in the active region, the gate electrodes having a substantially vertical shape, a lower portion of each of the gate electrodes disposed below a top surface of the semiconductor substrate, the lower portion of each of the gate electrodes representing a majority of the gate electrode;
• a gate insulation layer, the gate insulation layer in physical contact with the lower portion of the gate electrodes and in physical contact with the semiconductor substrate from the top surface of the semiconductor substrate to a bottom surface of the gate electrodes;
• a gate spacer, the gate spacer in physical contact with a remainder of the lower portion of the gate electrodes that is not in physical contact with the gate insulation layer;
• a first contact plug, the first contact plug surrounded by the gate spacer and in physical contact with the gate spacer, the first contact plug electrically connecting an upper conductive line with the semiconductor substrate;
• a plug impurity layer, the plug impurity layer disposed in a portion of the semiconductor substrate directly beneath the first contact plug;
• source/drain regions, the source/drain regions disposed opposite the gate electrodes in the active region of the semiconductor substrate;
• and
• a first insulation layer disposed on and physically touching the top surface of the semiconductor substrate and a top surface of the shallow trench insulator, the first insulation layer having a first gap, a width of the first gap defining a maximum width of a space occupied by the gate electrodes.