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US 7,408,222 B2Granted
Charge trapping device and method of producing the charge trapping device
AssigneeInfineon Technologies AG
InventorsRainer Hagenbeck, Christoph Ludwig, Mark Isler, Elard Stein von Kamienski
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Abstract
A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral direction towards a depletion region of the transistor is larger than the gradient in the vertical direction towards a well region.
Claims49
A semiconductor device comprising a field effect transistor formed on a semiconductor substrate, the semiconductor device comprising:
- a gate dielectric layer formed over a surface portion of the semiconductor substrate;
- a gate conductor, in contact with the gate dielectric layer, the gate conductor forming or being electrically connected to a word line;
- and
- a source and a drain region formed within the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer,
- wherein the source and drain region each comprise at least one implant region;
- wherein the at least one implant region has a first concentration profile of dopants in a vertical direction with respect to a substrate surface and a second concentration profile of dopants in a lateral direction with respect to the substrate surface;
- and
- wherein the second concentration profile in the lateral direction has a gradient, which is larger than a gradient of the first concentration profile in the vertical direction.
5 more elements
A semiconductor device comprising a field effect transistor formed on a semiconductor substrate, comprising:
- a gate dielectric layer formed over a surface portion of the semiconductor substrate;
- a gate conductor, in contact with the gate dielectric layer, the gate conductor forming or being electrically connected to a word line;
- and
- a source and a drain region formed within the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer;
- wherein the source and drain region each comprise at least two implant regions overlapping each other;
- wherein a concentration of dopants and a lateral dimension of a highly doped one of the overlapping implant regions is larger than that of a lightly doped one of the implant regions;
- and
- wherein a vertical dimension of the highly doped implant region is smaller than that of the lightly doped implant region, such that a pn-junction of the source or drain regions having a strong gradient of dopant concentration extends laterally towards a depletion region of the transistor and a respective pn-junction having a weak gradient of dopant concentration extends vertically towards a well region.
5 more elements
A method of producing a semiconductor device, the method comprising:
- providing a semiconductor substrate having a surface portion covered by a gate dielectric layer for trapping charges and a stack including a gate electrode formed on the gate dielectric layer;
- and
- performing an implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer, to form source and drain regions, which each include an implant region that has a dopant concentration profile, such that a pn-junction with a strong gradient of dopant concentration extends laterally towards a depletion region of the transistor and a pn-junction with a weak gradient of dopant concentration extends vertically towards a well region.
A method of producing a semiconductor device, the method comprising:
- providing a semiconductor substrate having a surface portion covered by a gate dielectric layer for trapping charges and a stack including a gate electrode formed on the gate dielectric layer;
- performing a first implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer, to form source and drain regions, which include a highly doped implant region that has a dopant concentration, a lateral and a vertical dimension;
- forming spacers at sidewalls of the stack including the gate electrode in order to cover a surface portion of highly doped implant region;
- and
- thereafter performing a second implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the additional spacers, to form source and drain regions, which further include a lightly doped implant region, which has a dopant concentration and a lateral dimension smaller than that of the highly doped implant region, a vertical dimension larger than that of the highly doped implant region, such that a pn-junction with a strong gradient of dopant concentration extends laterally towards a depletion region of the transistor and a pn-j unction with a weak gradient of dopant concentration extends vertically towards a well region.
2 more elements
Method of producing a semiconductor device, the method comprising
- providing a semiconductor substrate having a surface portion covered by a gate dielectric layer for trapping charges and a stack including a gate electrode formed on the gate dielectric layer;
- performing a first implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer, to form source and drain regions, which include a highly doped implant region that has a dopant concentration, a lateral and a vertical dimension;
- applying a thermal diffusion process to increase the lateral dimension of the highly doped implant region;
- thereafter performing a second implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the additional spacers, to form source and drain regions, which further include a lightly doped implant region, which has a dopant concentration and a lateral dimension smaller than that of the highly doped implant region, a vertical dimension larger than that of the highly doped implant region, such that a pn-junction with a strong gradient of dopant concentration extends laterally towards a depletion region of the transistor and a pn-j unction with a weak gradient of dopant concentration extends vertically towards a well region.
1 more element
Dependencies are inferred from the claim text.