Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region

A method of making a memory device on a semiconductor substrate of a first conductivity type, comprising:

• forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions;
• forming a conductive select gate over and insulated from a first portion of the channel region;
• forming a conductive floating gate having a bottom surface disposed over and insulated from the first region and a second portion of the channel region, wherein the floating gate formation includes forming a notch in the bottom surface having an edge that is aligned with an edge of the first region or that is disposed over the first region;
• and
• forming a conductive control gate having a first portion disposed adjacent to the floating gate;
• wherein the formation of the floating gate includes:
• forming insulation material of varying thickness over the substrate;
• and
• forming conductive material over the insulation material.

A method of making a memory device on a semiconductor substrate of a first conductivity type, comprising:

• forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions, and wherein the channel region includes a first portion adjacent the first region and a second portion adjacent the second region;
• forming a conductive select gate over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion;
• forming a conductive floating gate having a first portion disposed entirely over and insulated from the first region for generating fringing fields that control a conductivity of the channel region first portion, wherein the floating gate first portion including a bottom surface disposed entirely over and insulated from the first region and a side surface extending from the bottom surface and away from the substrate;
• and
• forming a conductive control gate having a first portion disposed adjacent to the floating gate.