Field effect transistor and method for manufacturing the same

A method of manufacturing a semiconductor device, the method comprising:

• forming fin active regions, which are distanced from each other and which are protruded from an upper surface of a lower layer supporting an upper layer of a semiconductor substrate;
• forming an interlayer dielectric layer on first and second active regions of both ends of the fin active region to expose a center portion of the fin active region;
• ion implanting an impurity to form a buried impurity region with a depth equal to or similar to a height of the fin active region, in the center portion of the fin active region, using the interlayer dielectric layer as an ion implantation mask;
• forming a third active region of a bridge shape, which is connected with the first and second active regions and which is distanced vertically from the lower layer, by selectively removing the buried impurity region;
• forming a gate insulation layer surrounding the third active region;
• forming a gate electrode on the gate insulation layer so that the third active region functions as a channel;
• removing the interlayer dielectric layer from the first and second active regions;
• and
• ion implanting a conductive impurity in the first and second active regions to form a source/drain impurity region by using the gate electrode as an ion implantation mask.

A method of manufacturing an FET, the method comprising:

• forming first and second active regions distanced from each other on an insulation layer;
• forming a third active region of a bridge shape, which is distanced vertically from an upper surface of the insulation layer and which connects the first and second active regions, the first, second, and third active regions formed from a single-crystal silicon layer;
• forming a gate insulation layer to surround the third active region;
• and
• forming a gate electrode on the gate insulation layer so that the third active region functions as a channel.

A method of manufacturing an FET, the method comprising:

• forming a fin active region on a substrate insulation layer of an SOI type silicon substrate;
• forming an interlayer dielectric layer on first and second active regions of both ends of the fin active region, to expose a center portion of the fin active region;
• forming a buried impurity region with a depth equal or similar to a height of the fin active region, in a center portion of the fin active region, by ion implanting an impurity by using the interlayer dielectric layer as an ion implantation mask;
• forming a channel impurity region of a bridge shape, which is connected with the first and second active regions and is distanced vertically from the substrate insulation layer, by selectively removing the buried impurity region;
• forming a gate insulation layer surrounding the third active region;
• forming a gate electrode on the gate insulation layer so that the third active region functions as a channel;
• removing the interlayer dielectric layer from the first and second active regions;
• and
• ion implanting a conductive impurity in the first and second active regions to form a source/drain impurity region by using the gate electrode as an ion implantation mask.