Planar dual gate semiconductor device

Abstract

A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.

Dependencies are inferred from the claim text.