Four-transistor Schmitt trigger inverter

A method for forming a four-transistor Schmitt trigger inverter, the method comprising:

• forming a two-transistor variable threshold level inverter including:
• forming an NMOS dual-gate thin-film transistor (DG-TFT) with a top gate, a bottom gate, source/drain (S/D) regions, a channel having a channel width underlying the top gate, and a dielectric thickness between the channel and the bottom gate;
• forming a PMOS DG-TFT with a top gate, a bottom gate, S/D regions, a channel having a channel width underlying the top gate, and a dielectric thickness between the channel and the bottom gate;
• forming a NMOS TFT;
• forming a PMOS TFT;
• connecting an NMOS TFT gate to an NMOS DG-TFT first S/D region, a PMOS DG-TFT first S/D region, and a PMOS TFT gate;
• connecting an NMOS TFT first S/D region to the NMOS DG-TFT back gate, the PMOS DG-TFT back gate, and a PMOS TFT first S/D region;
• setting a circuit first switch point in response to the DG-TFT channel widths;
• and,
• setting a circuit second switch point, lower than the first switch point, in response to the dielectric thicknesses between the channels and the bottom gates.