Line layout structure of semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsHyang-Ja Yang, Yun-Jin Jo
Life of this patent
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Abstract
A line layout structure of semiconductor memory device comprises first metal wire lines forming a bit line coupled to a memory cell, second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section word line electrically coupled to the memory cell, and third metal wire lines disposed substantially parallel to the second metal wire lines and over the second metal wire lines, the third metal wire lines forming a first power line or signal line.
Claims19
A line layout structure of semiconductor memory device having a plurality of memory cells, the structure comprising:
- first metal wire lines forming a bit line electrically coupled to the memory cell;
- second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section word line electrically coupled to the memory cell;
- and
- third metal wire lines disposed substantially parallel to the second metal wire lines and over the second metal wire lines, the third metal wire lines forming a first power line and a signal line.
A line layout structure of semiconductor memory device having a plurality of memory cells, the structure comprising:
- first metal wire lines forming a bit line electrically coupled to the memory cell;
- second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section word line electrically coupled to a word line coupled with the memory cell;
- and
- third metal wire lines disposed substantially parallel to the second metal wire lines and over the second metal wire lines, the third metal wire lines forming a main word line electrically coupled to an input terminal of a section row decoder for selecting the section word line, a first power line for supplying power source, and a signal line to receive signals for operation of the memory device.
Dependencies are inferred from the claim text.