Protection circuit against electrostatic discharge in semiconductor device

An electrostatic discharge protection circuit for use in a semiconductor device, comprising:

• an electrostatic signal discharge unit for discharging an electrostatic signal, the electrostatic signal discharge unit including a first NMOS transistor receiving an electrostatic detection voltage through its gate;
• a first electrostatic detection voltage supplying unit for generating the electrostatic detection voltage in response to an alternating current component of the electrostatic signal;
• a driving unit for generating a driving voltage in response to the electrostatic detection voltage in order to drive the electrostatic signal discharge unit;
• and
• a second electrostatic detection voltage supplying unit enabled in response to the driving voltage for continuously supplying the electrostatic detection voltage to the driving unit in response to a direct current component of the electrostatic signal, the second electrostatic detection voltage supplying unit including a second NMOS transistor;
• wherein the driving unit includes:
• a PMOS transistor whose one terminal and the other terminal are respectively coupled to the power supply voltage and gates of the first and the second NMOS transistors, wherein a gate of the PMOS transistor receives the electrostatic detection voltage;
• and
• a first resistor connected between the other terminal of the PMOS transistor and ground voltage, wherein a gate of the second NMOS transistor is directly coupled to a common node between the PMOS transistor and the first resistor of the driving unit, wherein the common node is coupled to the gate of the first NMOS transistor.