Semiconductor memory

A semiconductor memory comprising:

• a charge-trapping element arranged over a semiconductor body, the charge-trapping element comprising a nitride layer sandwiched between a bottom oxide layer and a top oxide layer, the charge-trapping element having two lateral sidewalls opposed to one another, wherein the nitride layer comprises sidewalls that are recessed with respect to sidewalls of the bottom oxide layer and of the top oxide layer, a first recess disposed on the respective sidewalls of the nitride layer wherein portions of the bottom oxide layer and the top oxide layer laterally extend beyond the nitride layer;
• a second recess disposed in the bottom oxide layer, wherein the second recess is not disposed directly under the first recess, and wherein the second recess does not expose a surface of the semiconductor body;
• a gate stack arranged over the charge-trapping element, the gate stack having two lateral sidewalls opposed to one another;
• electrically insulating elements disposed directly upon the opposing sidewalls of the charge-trapping element and covering the sidewalls of the charge-trapping element and only a portion of the sidewalls of the gate stack, wherein the electrically insulating elements comprise oxide layers;
• and
• nitride spacers covering the electrically insulating elements, wherein the nitride spacers are arranged on opposing sidewalls of the gate stack and on the electrically insulating elements.

A semiconductor memory comprising:

• a charge-trapping element arranged over a semiconductor body, the charge-trapping element comprising a nitride layer sandwiched between a bottom oxide layer and a top oxide layer, the charge-trapping element having two lateral sidewalls opposed to one another, wherein the nitride layer comprises sidewalls that are recessed with respect to sidewalls of the bottom oxide layer and of the top oxide layer,
• a first recess disposed on the respective sidewalls of the nitride layer and by portions of the bottom oxide layer and the top oxide layer laterally extending beyond the nitride layer;
• a second recess disposed in the bottom oxide layer, wherein the second recess is not disposed directly under the first recess, and wherein the second recess does not expose a surface of the semiconductor body;
• a gate stack arranged over the charge-trapping element, the gate stack having two lateral sidewalls opposed to one another;
• a thermal oxide layer disposed directly upon the opposing sidewalls of the top oxide of the charge-trapping element and covering the sidewalls of only a portion of the sidewalls of the gate stack, wherein the thermal oxide layer is thinner over the sidewalls of the top oxide than over the sidewalls of the gate stack;
• a deposited oxide disposed directly upon the opposing sidewalls of the nitride layer and the bottom oxide layer of the charge-trapping element, wherein the deposited oxide also disposed over the thermal oxide layer;
• and
• nitride spacers covering the electrically insulating elements, wherein the nitride spacers are arranged on opposing sidewalls of the gate stack and on the electrically insulating elements.