US 7,405,090 B2Granted

Method of measuring an effective channel length and an overlap length in a metal-oxide semiconductor field effect transistor

AssigneeSamsung Electronics Co., Ltd.

InventorYong-Un Jang

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Abstract

In a method of measuring an effective channel length and an overlap length, first to third metal-oxide semiconductor field effect transistors (MOSFETs) including first to third gate patterns, respectively, are formed on a substrate. A parasitic capacitance between the gate patterns and the substrate in the MOSFETs is determined based on first and second capacitances, which are measured by applying a first voltage between the gate patterns and the substrate. A second voltage is applied between the first gate pattern and the substrate in the first MOSFET and a third voltage between the third gate pattern and the substrate in the third MOSFET to measure capacitances. The capacitances are treated to obtain third and fourth capacitances excluding the parasitic capacitance. Overlap lengths of the gate patterns are obtained based on the third and fourth capacitances. Effective channel lengths of the gate patterns are obtained based on the overlap length.

Claims20

Dependent claims

A method of measuring an effective channel length and an overlap length in a MOSFET, comprising:

forming a first MOSFET, a second MOSFET and a third MOSFET on a substrate, the first MOSFET including a first gate pattern that has a first length and a first effective width, the second MOSFET including a second gate pattern that has the first length and a second effective width different from the first effective width, and the third MOSFET including a third gate pattern that has a second length different from the first length and a third effective width;
obtaining a parasitic capacitance between the first, second and third gate patterns and the substrate in the first, second, and third MOSFETs based on first and second capacitances, which are measured by applying a first voltage between the first and second gate patterns and the substrate;
applying a second voltage between the first gate pattern and the substrate in the first MOSFET and a third voltage between the third gate pattern and the substrate in the third MOSFET to measure a preliminary third capacitance and a preliminary fourth capacitance;
determining a third capacitance and a fourth capacitance by excluding the parasitic capacitance from the preliminary third capacitance and the preliminary fourth capacitance;
determining overlap lengths of the first, second and third gate patterns based on the third and fourth capacitances;
and
determining effective channel lengths of the first, second and third gate patterns based on the overlap length.

4 more elements

A method of measuring an effective channel length and an overlap length in a MOSFET, comprising:

forming a first MOSFET, a second MOSFET and a third MOSFET on a substrate, the first MOSFET including a first gate pattern that has N number of gate fingers having a first length and a first width, the second MOSFET including a second gate pattern that has M number of gate fingers having the first length and the first width, and the third MOSFET including a third gate pattern that has L number of gate fingers having a second length and the first width;
determining a parasitic capacitance between the first, second and third gate patterns and the substrate in the first, second and third MOSFETs, based on first and second capacitances, which are measured by applying a first voltage between the first and second gate patterns and the substrate and a capacitance obtained when the number of the gate fingers is approximately zero;
determining the second and third voltages as voltages obtained when carriers reach junction boundaries of the first and third MOSFETs, respectively;
applying the second voltage between the first gate pattern and the substrate in the first MOSFET and the third voltage between the third gate pattern and the substrate in the third MOSFET and measuring a preliminary third capacitance and a preliminary fourth capacitance;
determining a third capacitance and a fourth capacitance by excluding the parasitic capacitance from the preliminary third and fourth capacitances to obtain;
calculating a gate length, when capacitances between the first, second and third gate patterns and the substrate are approximately zero, based on the third and fourth capacitances;
multiplying the gate length by ½ to obtain an overlap length;
and
determining effective channel lengths of the first, second and third gate patterns based on the overlap length.

6 more elements

Dependencies are inferred from the claim text.