Method for analyzing fail bit maps of waters and apparatus therefor
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Matsushita, Kenichi Kadota, Kenji Kawabata, Yoshiyuki Shioyama
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AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Matsushita, Kenichi Kadota, Kenji Kawabata, Yoshiyuki Shioyama
Estimating the term…
A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.
A method for analyzing fail bit maps comprising:
Dependencies are inferred from the claim text.