Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction
AssigneeAdvanced Micro Devices, Inc.
InventorsGilles Amblard, Srikanteswara Dakshina-Murthy, Bhanwar Singh
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Abstract
The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit. Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.
Claims21
A system for mitigating line-edge roughness on a semiconductor device, comprising:
- a monitoring component that monitors information associated with an original distance of a photoresist and line-edge roughness on a photoresist;
- a non-lithographic shrink component comprising at least one of a chemical component, a shrink enhancement component that shrinks a gate channel, or a thermal component that applies heat to the photoresist to a point for causing the photoresist to just enter a liquid phase to mitigate line-edge roughness, which in turn increases a distance between gates and decreases a thickness of the photoresist layer;
- and
- a trim etch component is utilized to mitigate the increased distance between the gates by removing excess resist material resulting from the non-lithographic component so as to restore the original distance of the photoresist.
A method for mitigating line-edge roughness on a semiconductor device, comprising:
- determining whether line-edge roughness is extant on a patterned photoresist;
- employing a non-lithographic shrink technique comprising at least one of a chemical technique, an expansion technique, a shrink enhancement technique that shrinks a gate channel, or a thermal technique to heat a photoresist to a point for causing the photoresist to just enter a liquid phase to mitigate line-edge roughness, which in turn increases a distance between gates and decrease a thickness of the photoresist layer;
- and
- employing a trim etch technique to mitigate the increased distance between the gates by removing excess resist material resulting from the non-lithographic component so as to restore an original distance of the photoresist.
A system for mitigating line-edge roughness on a semiconductor device, comprising:
- means for determining critical dimensions and line-edge roughness on a photoresist;
- means for employing a non-lithographic shrink technique comprising at least one of a chemical technique, an expansion technique, a shrink enhancement technique that shrinks a gate channel, or a thermal technique to heat a photoresist to a point for causing the photoresist to just enter a liquid phase to mitigate line-edge roughness, which in turn increases a distance between gates and decreases a thickness of the photoresist layer;
- and
- means for removing excess resist material resulting from the non-lithographic shrink technique to restore an original distance of the photoresist.
Dependencies are inferred from the claim text.