Back to results
US 7,402,889 B2Granted
Semiconductor device and method for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorDuk-Seo Park
Life of this patent
Estimating the term…
Abstract
Disclosed is a metal-insulator-metal (MIM) capacitor structure formed by a metal interconnection process of trench-exposed metal layers formed on stacked interlayer insulating layers. The MIM capacitor uses a conductive layer conformally formed on the metal interconnection and/or trench regions to enlarge constituent electrode surface areas.
Claims34
A semiconductor device comprising:
- a first metal pattern formed on a semiconductor substrate;
- a first interlayer insulating layer formed on the first metal pattern;
- a second metal pattern formed on the first interlayer insulating layer;
- a second interlayer insulating layer formed on the second metal pattern;
- a dielectric layer and conductive layer formed on sidewalls of a first trench formed in the second interlayer insulating layer, the first trench selectively exposing a significant portion of the second metal pattern, and the dielectric layer also being formed on the significant portion of the second metal pattern and on sidewall portions of a second trench formed in the first interlayer insulating layer, the second trench exposing a significant portion of the first metal pattern, and the dielectric layer also being formed on the significant portion of the first metal pattern;
- wherein the second trench is formed self-aligned using the second metal pattern as a mask;.and
- a third metal pattern formed on the dielectric layer and conductive layer.
4 more elements
A method for manufacturing a semiconductor device comprising:
- forming a first metal pattern on a substrate;
- forming a first interlayer insulating layer on the first metal pattern;
- forming a second metal pattern on the first interlayer insulating layer;
- forming a second interlayer insulating layer on the second metal pattern;
- forming a first trench in the second interlayer insulating layer to expose a significant portion of the second metal pattern;
- forming a second trench in the first interlayer insulating layer using the second metal pattern as an etch mask to expose a significant portion of the first metal pattern;
- forming a dielectric layer and a conductive layer on the sidewalls of the first and second interlayer insulating layers formed by the first and second trenches, and on the exposed significant portions of the first and second metal patterns;
- and
- forming a third metal pattern on the dielectric layer and the conductive layer.
6 more elements
A method for manufacturing a semiconductor device comprising:
- forming a first metal interconnection and a first metal pattern on a substrate;
- forming a first interlayer insulating layer on the first metal interconnection and the first metal pattern;
- forming a second contact plug electrically connected with the first metal interconnection through the first interlayer insulating layer;
- forming a second metal pattern having a first opening and a second metal interconnection electrically connected with the second contact plug;
- forming a second interlayer insulating layer;
- patterning the second interlayer insulating layer to form a first trench exposing the second metal pattern and a third contact hole exposing the second metal interconnection;
- etching the first interlayer insulating layer exposed by the first opening using the exposed second metal pattern as an etch mask to form a second trench exposing the first metal pattern;
- forming a conductive layer in the first and second trenches and in the third contact hole;
- forming a dielectric layer in the first and second trenches;
- forming a third metal pattern in the first and second trenches.
7 more elements
A method for manufacturing a semiconductor device comprising:
- simultaneously forming a first interconnection and a first metal pattern on a substrate;
- forming a first interlayer insulating layer on the first metal interconnection and the first metal pattern;
- simultaneously forming a second metal pattern having a first opening and a second metal interconnection;
- forming a second interlayer insulating layer on the second metal pattern and the second metal interconnection;
- patterning the second interlayer insulating layer to form a first trench exposing a significant portion of the second metal pattern and a third contact hole exposing the second metal interconnection;
- etching a first interlayer insulating layer exposed by the first opening using the exposed second metal pattern as an etch mask to form a second trench exposing the first metal pattern;
- forming a lower conductive layer conformally in the first and second trenches and filling the third contact hole;
- forming a dielectric layer and an upper conductive layer on the lower conductive layer;
- and
- planarizing the upper conductive layer, the dielectric layer and the lower conductive layer until the second interlayer insulating layer is exposed to form a metal-insulator-metal capacitor in the first and the second trench and a third contact plug in the third contact hole.
7 more elements
A semiconductor device comprising:
- a first metal pattern formed on a substrate;
- a first interlayer insulating layer including a second trench exposing the first metal pattern;
- a second metal pattern disposed on a first interlayer insulating layer around the second trench;
- a second interlayer insulating layer disposed on the first interlayer insulating layer and the second metal pattern and having a first trench exposing a part of the second metal pattern around the second trench;
- a dielectric layer and a conductive layer formed on the sidewalls of the first and the second interlayer insulating layer in the first and the second trench and on the first and the second metal pattern;
- and
- a third metal pattern formed on the dielectric layer, the conductive layer and the second interlayer insulating layer.
4 more elements
Dependencies are inferred from the claim text.