Memory cells and select gates of NAND memory arrays

A NAND memory array comprising:

• a plurality of rows of memory cells;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a select gate of the respective column, the select gates of the respective columns and each of the memory cells comprising:
• a first dielectric layer formed on a semiconductor substrate of the memory array;
• a first conductive layer formed on the first dielectric layer;
• conductive spacers formed on sidewalls of the first conductive layer and located between an upper surface of the first conductive layer and the first dielectric layer;
• a second dielectric layer overlying the first conductive layer and the conductive spacers;
• a second conductive layer formed on the second dielectric layer;
• and
• a third conducive layer formed on the second conductive layer;
• wherein the third conductive layer of the select gate passes though a portion of the second conductive layer and the second dielectric layer of the select gate so that a portion of the third conductive layer of the select gate contacts the first conductive layer of the select gate, the third conductive layer of the select gate electrically connecting the first and second conductive layers of the select gate, wherein the portion of the third conductive layer of the select gate that contacts the first conductive layer of the select gate is interposed between first and second portions of the second dielectric layer of the select gate.

A NAND memory array comprising:

• a plurality of rows of memory cells;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column and selectively connected to a source line through a source select gate of the respective column, the drain and source select gates of the respective columns and each of the memory cells comprising:
• a first dielectric layer formed on a semiconductor substrate of the memory array;
• a first conductive layer formed on the first dielectric layer;
• conductive spacers formed on sidewalls of the first conductive layer and located between an upper surface of the first conductive layer and the first dielectric layer;
• a second dielectric layer overlying the first conductive layer and the conductive spacers;
• a second conductive layer formed on the second dielectric layer;
• and
• a third conducive layer formed on the second conductive layer;
• wherein the third conductive layer of each of the drain and source select gates passes though a portion of the second conductive layer and the second dielectric layer of that select gate so that a portion of the third conductive layer of that select gate contacts the first conductive layer of that select gate, the third conductive layer of that select gate electrically connecting the first and second conductive layers of that select gate, wherein the portion of the third conductive layer of that select gate that contacts the first conductive layer of that select gate is interposed between first and second portions of the second dielectric layer of that select gate.

A memory device comprising:

• a memory array comprising:
• a plurality of rows of memory cells, each row connected to a word line;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a select gate of the respective column, the select gates of the respective columns and each of the memory cells comprising:
• a first dielectric layer formed on a semiconductor substrate of the memory device;
• a first conductive layer formed on the first dielectric layer;
• conductive spacers formed on sidewalls of the first conductive layer and located between an upper surface of the first conductive layer and the first dielectric layer;
• a second dielectric layer overlying the first conductive layer and the conductive spacers;
• a second conductive layer formed on the second dielectric layer;
• and
• a third conducive layer formed on the second conductive layer;
• wherein the third conductive layer of the select gate passes though a portion of the second conductive layer and the second dielectric layer of the select gate so that a portion of the third conductive layer of the select gate contacts the first conductive layer of the select gate, the third conductive layer of the select gate electrically connecting the first and second conductive layers of the select gates, wherein the portion of the third conductive layer of the select gate that contacts the first conductive layer of the select gate is interposed between first and second portions of the second dielectric layer of the select gate;
• column access circuitry connected to the bit lines;
• and
• row access circuitry connected to the word lines.

A memory device comprising:

• a memory array comprising:
• a plurality of rows of memory cells, each row connected to a word line;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column and selectively connected to a source line through a source select gate of the respective column, the drain and source select gates of the respective columns and each of the memory cells comprising:
• a first dielectric layer formed on a semiconductor substrate of the memory device;
• a first conductive layer formed on the first dielectric layer;
• conductive spacers formed on sidewalls of the first conductive layer and located between an upper surface of the first conductive layer and the first dielectric layer;
• a second dielectric layer overlying the first conductive layer and the conductive spacers;
• a second conductive layer formed on the second dielectric layer;
• and
• a third conducive layer formed on the second conductive layer;
• wherein the third conductive layer of each of the drain and source select gates passes though a portion of the second conductive layer and the second dielectric layer of that select gate so that a portion of the third conductive layer of that select gate contacts the first conductive layer of that select gate, the third conductive layer of that select gate electrically connecting the first and second conductive layers of that select gate, wherein the portion of the third conductive layer of that select gate that contacts the first conductive layer of that select gate is interposed between first and second portions of the second dielectric layer of that select gate;
• column access circuitry connected to the bit lines;
• and
• row access circuitry connected to the word lines.