Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same

A system comprising:

• a microelectronic assembly including:
• a non-planar microelectronic device comprising:
• a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof;
• a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion;
• a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion;
• a gate electrode on the device isolation layer and further extending on the gate dielectric layer;
• an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion, wherein the device isolation layer defines side recesses on each side of the fin, and wherein the pate electrode extends into the side recesses to define corresponding recess electrode portions;
• and
• a main memory coupled to the microelectronic assembly.