Method for fabricating high voltage semiconductor device
AssigneeOki Electric Industry Co., Ltd.
InventorTsukasa Yajima
Life of this patent
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Abstract
A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising: forming a mask pattern on the semiconductor substrate; forming a first low-density impurity implanted region on the semiconductor substrate using the mask pattern, in which the first low-density impurity implanted region is overlapped with the gate electrode; selectively removing a part of the mask pattern from a region where the gate electrode is to be formed to form a gate-formation mask; and forming the gate insulating layer and the gate electrode using the gate-formation mask.
Claims11
A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate;
- a gate insulation layer formed on the semiconductor substrate;
- and a gate electrode formed on the gate insulation layer, comprising:
- forming a mask pattern on the semiconductor substrate;
- forming a first low-density impurity implanted region on the semiconductor substrate using the mask pattern, in which the first low-density impurity implanted region is overlapped with the gate electrode;
- selectively removing a part of the mask pattern from a region where the gate electrode is to be formed to form a gate-formation mask;
- forming the gate insulating layer and the gate electrode using the gate formation mask;
- removing the gate-formation mask after the gate electrode is formed;
- and
- forming a second low-density impurity implanted region on the semiconductor substrate so that the second low-density impurity implanted region is located outside the first low-density impurity implanted region.
A method for fabricating a high voltage MOS transistor, which comprises a semiconductor substrate;
- a gate insulation layer formed on the semiconductor substrate;
- and a gate electrode formed on the gate insulation layer, comprising:
- forming a mask pattern on the semiconductor substrate;
- forming a first low-density impurity implanted region on the semiconductor substrate using the mask pattern, in which the first low-density impurity implanted region is overlapped with the gate electrode;
- selectively removing a part of the mask pattern from a region where the gate electrode is to be formed to form a gate-formation mask;
- forming the gate insulating layer and the gate electrode using the gate-formation mask;
- removing the gate-formation mask after the gate electrode is formed;
- forming a second low-density impurity implanted region on the semiconductor substrate so that the second low-density impurity implanted region is located outside the first low-density impurity implanted region;
- and
- forming a high-density impurity implanted region after the second low-density impurity-implanted region is formed, the high-density impurity implanted region having a higher density of impurity than the first and second low-density impurity-implanted regions.
Dependencies are inferred from the claim text.