Method for forming an electronic device
AssigneeFreescale Semiconductor, Inc.
InventorsMarius K. Orlowski, Brian J. Goolsby
Life of this patent
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Abstract
An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.
Claims20
A process for forming an electronic device comprising:
- forming a first layer overlying a first plurality of transistor locations of a device substrate, wherein each of the first plurality of transistor locations comprises a gate structure and source/drain locations, wherein the gate structure comprises a conductive gate structure and a sidewall structure;
- forming a second layer overlying the first layer;
- etching a first portion of the first layer and the second layer to expose source/drain material comprising a semiconductor element at the source/drain locations of a second plurality of transistor locations and leaving a second portion of the second layer overlying a third plurality of transistor locations, wherein the first plurality of transistor locations comprise the second and third plurality of transistor locations;
- etching the exposed source/drain material and the second portion of the second layer simultaneously, wherein etching of the exposed source/drain material is end-point-terminated based upon removal of the second layer;
- and
- forming a third layer at the source/drain locations of the second plurality of transistor locations after etching the exposed source/drain material, wherein the third layer is formed epitaxially to have a same lattice structure and a different intrinsic lattice spacing as the exposed source/drain material.
A process for forming an electronic device comprising:
- forming a first layer overlying a first plurality of transistor locations of a device substrate, wherein each of the first plurality of transistor locations comprises a gate structure comprising a conductive gate structure overlying a semiconductor element on insulator (SOI) substrate, a sidewall structure, and a source/drain location;
- forming a second layer overlying the first layer, wherein a thickness of the second layer is greater than a thickness of the first layer;
- etching a first portion of the first layer and the second layer to expose source/drain material comprising a semiconductor element at the source/drain locations of a second plurality of transistor locations and leaving a second portion of the second layer overlying a third plurality of transistor locations, wherein the first plurality of transistor locations comprise the second and third plurality of transistor locations;
- etching the exposed source/drain material and the second portion of the second layer simultaneously, wherein etching of the exposed source/drain material is end-point-terminated based upon removal of a substantial portion of the second portion of second layer;
- and
- forming a third layer at the source/drain locations of the second plurality of transistor locations after etching the exposed source/drain material, wherein the third layer is formed epitaxially to have a same lattice structure and a different intrinsic lattice spacing as the exposed source/drain material to provide a compressive stress at a channel location of the second plurality of transistor locations.
Dependencies are inferred from the claim text.