Micro-coded processors for concurrent processing in a programmable logic device

An integrated circuit having programmable logic, comprising:

• thread-specific processors coupled to one another and instantiated in the programmable logic responsive to a multi-threaded application;
• instruction memory for storing source and destination address information coupled to the thread-specific processors;
• data memory for storing data values and data results coupled to the thread-specific processors;
• each of the thread-specific processors including a data movement engine and a compute engine;
• the source and destination address information being associated with a sequence of data operations to be performed by the thread-specific processors on the data values stored to produce the data results, the thread-specific processors in combination with the sequence of data operations as associated with the source and destination address information providing micro-coded processors for concurrent processing;
• wherein the sequence of data operations associated with the source and destination address information for fetch-execution cycles of the thread-specific processors being executable without explicit instructions;
• and
• wherein implicit move instructions are within the source and destination address information being ordered to preserve the sequence of data operations for execution without move instruction decoding.

A system for concurrent data processing, comprising:

• thread-specific processors coupled to one another and instantiated in programmable logic responsive to a multi-threaded application, the multi-threaded application parsed into respective threads, the threads having data value variables, data operators, data processing order of execution, and data result variables;
• the thread-specific processors instantiated from a configuration bitstream, the configuration bitstream provided by,
• conversion of the threads into a code listing;
• associating source address information with the data value variables in the code listing;
• associating destination address information with the data result variables in the code listing;
• associating the source address information and the destination address information to provide source and destination address information;
• ordering the source and destination address information to preserve the data processing order of execution;
• instruction memory for storing the source and destination address information, the instruction memory coupled to the thread-specific processors;
• data memory for storing data values associated with the data value variables and for storing data results associated with the data result variables, the data memory coupled to the thread-specific processors;
• each of the thread-specific processors including a data movement engine and a compute engine;
• the thread-specific processors in combination with the source and destination address information as ordered providing micro-coded processors for concurrent processing without having to decode instructions;
• wherein the data processing order of execution is associated with the source and destination address information for fetch-execution cycles of the thread-specific processors being executable without explicit instructions;
• and
• wherein implicit move instructions are within the source and destination address information being ordered to preserve the data processing order of execution for execution without move instruction decoding.