Gate electrode architecture for improved work function tuning and method of manufacture

A semiconductor device having a first well of a first conductivity type and a second well of a second conductivity type, the semiconductor device comprising:

• gate dielectric layer means extending over at least a portion of the first well and the second well;
• first gate electrode means disposed on the gate dielectric layer means and extending over the first well, the first gate electrode means comprising a multi-layer stack, comprising:
• (i) a first thin metal/metal nitride layer disposed on the gate dielectric layer;
• (ii) a second thin metal/metal nitride layer disposed on the first thin metal/metal nitride layer;
• (iii) a third thin metal/metal nitride layer disposed on the second thin metal/metal nitride layer;
• and
• (iv) a first thick metal/metal nitride layer disposed on the third thin metal/metal nitride layer
• first source electrode means and first drain electrode means formed in the first well adjacent to the first gate electrode means;
• second gate electrode means disposed on the gate dielectric layer and extending over the second well, the second gate electrode means comprising a portion of the first thick metal/metal nitride layer;
• and
• second source electrode means and second drain electrode means formed in the second well adjacent to the second gate electrode means,
• wherein the first, second, and third thin metal/metal nitride layers are of an amorphous form and the first thick metal/metal nitride layer is of a polycrystalline form.