Method and system for reducing inter-layer capacitance in integrated circuits
AssigneeLSI Corporation
InventorsKunal N. Taravade, Neal Callan, Paul G. Filseth
Life of this patent
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Abstract
The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.
Claims19
A method for placing dummy fill patterns in an integrated circuit fabrication process, comprising:
- obtaining layout information of the integrated circuit, the integrated circuit including a plurality of layers;
- obtaining a first dummy fill space for a first layer based on the layout information;
- obtaining a second dummy fill space for a second layer, the second layer being placed successively to the first layer;
- determining an overlap between the first dummy fill space and the second dummy fill space;
- and
- minimizing the overlap by re-arranging a plurality of first dummy fill features and a plurality of second dummy fill features,
- wherein the first dummy fill space includes non-signal carrying lines on the first layer and the second dummy fill space includes non-signal carrying lines on the second layer.
A method of filling dummy patterns for pattern density equalization in an integrated circuit fabrication process, comprising:
- obtaining a local density pattern of a first layer, the local density pattern obtained based on an initial layout design of the integrated circuit;
- determining a second layer, the second layer being placed successively to the first layer;
- obtaining a local density pattern of the second layer, the local density pattern obtained based on the initial layout design of the integrated circuit;
- designing a plurality of dummy fill features on the first layer and the second layer, the plurality of dummy fill features being suitable for increasing pattern density in low density spaces on the first layer and the second layer;
- determining whether there is an overlap between the plurality of dummy fill features on the first layer and the plurality of dummy fill features on the second layer;
- and
- minimizing the overlap by re-arranging the plurality of dummy fill features on the first layer and the second layer,
- wherein a total inter-layer capacitance of the integrated circuit is minimized.
Dependencies are inferred from the claim text.