Method of forming shallow trench isolation
AssigneeDongbu Electronics Co., Ltd.
InventorJong-Woon Choi
Life of this patent
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Abstract
A method of manufacturing a semiconductor device including forming a pad oxide layer on a semiconductor substrate, forming a spacer oxide layer pattern on sidewalls of the pad oxide layer, and forming a nitride layer on the pad oxide layer. The method further includes forming a groove in the nitride layer by selectively removing the spacer oxide layer pattern, forming a trench in a region where the groove is formed, and filling the trench with a thermal oxide layer so as to form a shallow trench isolation (STI) layer. In the method, the line width of the STI layer depends on the thickness of the spacer oxide layer, and so the STI layer can be formed to a line width W smaller than a design rule.
Claims5
A method of manufacturing a semiconductor device, comprising:
- forming a pad oxide layer on a semiconductor substrate;
- forming a nitride layer pattern on the pad oxide layer;
- forming a spacer oxide layer pattern on the side wall of the nitride layer pattern;
- removing the nitride layer pattern so as to expose the spacer oxide layer pattern and the pad oxide layer;
- forming a nitride layer on the spacer oxide layer pattern and the pad oxide layer;
- forming a groove in the nitride layer by selectively removing the spacer oxide layer pattern;
- forming a trench in a region of the semiconductor substrate where the groove is formed above the region of the semiconductor substrate;
- and
- filling the trench with a thermal oxide layer so as to form a shallow trench isolation (STI) layer,
- wherein the formation of the spacer oxide layer pattern comprises:
- forming an oxide layer on the nitride layer pattern;
- and
- forming a spacer oxide layer pattern by anisotropically etching the oxide layer.
Dependencies are inferred from the claim text.