US 7,396,710 B2Granted

Fin-type semiconductor device with low contact resistance and its manufacture method

AssigneeFujitsu Limited

InventorMasaki Okuno

Life of this patent

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Abstract

A semiconductor device comprises a fin-type semiconductor region (fin) on a support substrate, having a pair of generally vertical side walls and an upper surface coupling the side walls; an insulated gate electrode structure traversing an intermediate portion of the fin and having side walls in conformity with the side walls of the fin; source/drain regions formed in the fin on both sides of the gate electrode; side wall insulating films including a first portion formed on the side walls of the conductive gate electrode and a second portion formed on the side walls of the fin and having an opening in the source/drain regions extending from an upper edge to a lower edge of each of the side walls; a silicide layer formed on each surface of the source/drain regions exposed in the opening of the second side wall insulating film; and source/drain electrodes contacting the silicide layers.

Claims10

Dependent claims

A semiconductor device manufacture method comprising the steps of:

(a) patterning a semiconductor layer of an SOI substrate to form a fin-type semiconductor region on a support substrate having an insulating surface, said fin-type semiconductor region having a pair of side walls generally vertical to a surface of said support substrate and an upper surface coupling said side walls;
(b) forming an insulated gate electrode structure traversing an intermediate portion of said fin-type semiconductor region and including a gate insulating film and a conductive gate electrode formed on said gate insulating film, said gate electrode having side walls in conformity with the side walls of said fin-type semiconductor region;
(c) forming a side wall insulating film on the side walls of said fin-type semiconductor region and on side walls of said insulated gate electrode structure;
(d) forming source/drain regions in said fin-type semiconductor region on both sides of said conductive gate electrode;
(e) depositing an interlayer insulating film covering said side wall insulating films;
(f) opening contact holes through said interlayer insulating film, said contact holes reaching said source/drain regions, and removing said side wall insulating films in said contact holes to expose said source/drain regions;
and
(g) forming a silicide layer on semiconductor surfaces in said contact holes.

5 more elements

A semiconductor device manufacture method comprising the steps of:

(a) patterning a semiconductor layer of an SOI substrate to form a fin-type semiconductor region on a support substrate having an insulating surface, said fin-type semiconductor region having a pair of side walls having a first height and being generally vertical to a surface of said support substrate and an upper surface coupling said side walls;
(b) forming an insulated gate electrode structure traversing an intermediate portion of said fin-type semiconductor region and including a gate insulating film and a conductive gate electrode formed on said gate insulating film, said gate electrode having side walls having a second height higher than said first height;
(c) forming a side wall insulating film covering said fin-type semiconductor region and said insulated gate electrode structure;
(d) forming source/drain regions in said fin-type semiconductor region on both sides of said insulated gate electrode structure;
(e) anisotropically etching said side wall insulating film to completely remove said side wall insulating film from the upper surface and the side walls of said fin-type semiconductor region, to remove said side wall insulating film from the upper surface and upper portions of the side walls of said gate electrode, and to leave said side wall insulating film on lower portions of the side walls of said gate electrode near said fin-type semiconductor region, said left side wall insulating film surrounding the upper surface and the side walls of said fin-type semiconductor region;
(f) forming a silicide layer at least on the exposed side walls, from upper edges to lower edges thereof, of said fin-type semiconductor region;
(g) depositing an interlayer insulating film covering said fin-type semiconductor region and said gate electrode;
(h) forming contact holes through said interlayer insulating film, said contact holes exposing said silicide layers on the side walls of said fin-type semiconductor region;
and
(i) burying conductive plugs in said contact holes.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/896,826Filed 6 Sep 2007 · division
Priority: JP 2005-00885417 Jan 2005
Published: US 2008/0003730 A13 Jan 2008
Granted: 8 Jul 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes
H10D
Inorganic electric semiconductor devices

Family

Application11/123,145Parent of this division · filed 6 May 2005
US 2008/0003730 A1Pre-grant publication · published 3 Jan 2008
US 7,282,766 B2Parent of this division
US 2006/0157749 A1Published application
US 7,396,710 B2This patent

From the US filing history. Foreign family members aren’t listed.