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US 7,376,931 B2Granted
Method for providing layout design and photo mask
AssigneeNEC Electronics Corporation
InventorTetsuya Kokubun
Life of this patent
Estimating the term…
Abstract
A method for providing the layout design of semiconductor integrated circuit that is capable of promoting the reduction of the circuit pattern area is provided. A hole pattern is disposed at the mesh point which is an intersecting point of mutually orthogonal virtual grid lines and another hole pattern is not disposed at the adjacent mesh point that is the closed mesh point having the hole pattern thereon.
Claims16
A method for providing a layout design for a semiconductor integrated circuit, comprising:
- disposing a hole pattern at a mesh point of orthogonally intersecting virtual grid lines of a virtual grid,
- wherein each adjacent mesh point is free of another hole pattern, said adjacent mesh point being closest to a hole mesh point, said hole mesh point having said hole pattern thereon.
A method for providing a layout design for a semiconductor integrated circuit, comprising:
- disposing a hole pattern at a mesh point, which is an intersecting point of mutually orthogonal virtual grid lines, wherein an interval of one of arrays disposed along the virtual grid lines in mutually orthogonal two directions is smaller than a resolution limit pitch of an exposure process for said semiconductor device and an interval of the other array thereof is a size equal to or larger than said resolution limit pitch, and wherein, when said hole pattern is disposed at a mesh point of said virtual grid, concerning the direction along said array having the interval smaller than said resolution limit pitch, no hole pattern is disposed at an adjacent mesh point that is closest to said mesh point having said hole pattern thereon.
Dependencies are inferred from the claim text.