Low loss interconnect structure for use in microelectronic circuits
AssigneeIntel Corporation
InventorsFrank O'Mahony, Mark A. Anders, Krishnamurthy Soumyanath
Life of this patent
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Abstract
A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
Claims18
A low loss interconnect structure on a microelectronic die, comprising:
- first and second differential signal lines formed on a first metal layer of the microelectronic die and configured to carry a differential signal within the microelectronic die, the first and the second differential signal lines being substantially parallel to one another, a selected one of the first and the second differential signal lines being operable to provide a return path for a signal on the other one of the first and the second differential signal lines, the structure further including a trace formed on a second metal layer proximate to the first metal layer, wherein the trace is non-conductively coupled and non-parallel to the first and second differential signal lines, and wherein the return path on the selected one of the first and second differential signal lines being a predominant return path for the signal.
Dependencies are inferred from the claim text.