Cascode, cascode circuit and method for vertical integration of two bipolar transistors into a cascode arrangement

A cascode comprising:

• a first transistor including a first base semiconductor region, a first collector semiconductor region, and a first emitter semiconductor region;
• and
• a second transistor including a second base semiconductor region, a second collector semiconductor region, and a second emitter semiconductor region,
• wherein the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor border on a buried conductive layer that electrically connects the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor with one another, and the first transistor and the second transistor are vertically integrated such that on junctions of the two transistors are substantially parallel to a surface of a wafer, and
• wherein at least one of the pn junctions is a heterojunction.

A cascode comprising:

• a first transistor including a first base semiconductor region, a first collector semiconductor region, and a first emitter semiconductor region;
• and
• a second transistor including a second base semiconductor region, a second collector semiconductor region, and a second emitter semiconductor region,
• wherein the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor border on a buried conductive layer that electrically connects the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor with one another,
• wherein the first collector semiconductor region of the first transistor has a thickness of less than 100 nm.

A cascode comprising:

• a first transistor including a first base semiconductor region, a first collector semiconductor region, and a first emitter semiconductor region;
• and
• a second transistor including a second base semiconductor region, a second collector semiconductor region, and a second emitter semiconductor region,
• wherein the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor border on a buried conductive layer that electrically connects the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor with one another,
• wherein the first collector semiconductor region of the first transistor has a dopant concentration of at least 1·1017 cm−3.

A cascode comprising:

• a first transistor including a first base semiconductor region, a first collector semiconductor region, and a first emitter semiconductor region;
• and
• a second transistor including a second base semiconductor region, a second collector semiconductor region, and a second emitter semiconductor region,
• wherein the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor border on a buried conductive layer that electrically connects the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor with one another,
• wherein the second emitter semiconductor region of the second transistor has a dopant concentration of at least 1·1018 cm−3.

A cascode comprising:

• a first transistor including a first base semiconductor region, a first collector semiconductor region, and a first emitter semiconductor region;
• and
• a second transistor including a second base semiconductor region, a second collector semiconductor region, and a second emitter semiconductor region,
• wherein the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor border on a buried conductive layer that electrically connects the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor with one another, and
• wherein the buried layer has highly doped silicon upon which rests, at least partly between the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor, or between the first emitter semiconductor region of the first transistor and the second collector semiconductor region of the second transistor, an ohmic silicide layer connected to the buried conductive layer of highly doped silicon.

A cascode comprising:

• a first transistor including a first base semiconductor region, a first collector semiconductor region, and a first emitter semiconductor region;
• and
• a second transistor including a second base semiconductor region, a second collector semiconductor region, and a second emitter semiconductor region,
• wherein the first emitter semiconductor region of the first transistor and the second collector semiconductor region of the second transistor are geometrically arranged on top with respect to a wafer surface, and
• wherein the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor are geometrically arranged on a bottom with respect to the wafer surface, and the second collector semiconductor region comprises a cascode output and the first base semiconductor region comprises a cascode input.

A cascode circuit comprising:

• a first transistor, which is connected in a common-emitter circuit;
• and
• a second transistor, which is connected in a common-base circuit,
• wherein a collector semiconductor region of the first transistor and an emitter semiconductor region of the second transistor border on a conductive buried layer that electrically connects the collector semiconductor region of the first transistor and the emitter semiconductor region of the second transistor with one another, wherein the buried layer has highly doped silicon upon which rests, at least partly between the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor, or between the first emitter semiconductor region of the first transistor and the second collector semiconductor region of the second transistor, an ohmic silicide layer connected to the buried conductive layer of highly doped silicon.

A cascade circuit comprising:

• a first transistor, which is connected in a common-emitter circuit;
• and
• a second transistor, which is connected in a common-base circuit,
• wherein a collector semiconductor region of the first transistor and an emitter semiconductor region of the second transistor border on a conductive buried layer that electrically connects the collector semiconductor region of the first transistor and the emitter semiconductor region of the second transistor with one another, and
• wherein a collector semiconductor region of the second transistor connected in a common-base circuit provides a cascade output and a base semiconductor region of the first transistor connected in the common-emitter circuit provides a cascade input.