Fuse region of a semiconductor region
AssigneeSamsung Electronics Co., Ltd.
InventorsHyuck-Jin Kang, Chang-Suk Hyun, Il-Young Moon, Kang-Yoon Lee, Kwang-bo Sim, Sang-Kil Jeon
Life of this patent
Estimating the term…
Abstract
In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses, and a plurality of fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer.
Claims9
A fuse region of a semiconductor device, comprising:
- an interlayer insulating layer on a semiconductor substrate;
- a plurality of fuses on the interlayer insulating layer in parallel with each other;
- a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses;
- and
- a plurality of insulating fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer;
- wherein the blocking layer includes a first insulating layer pattern and a second insulating layer pattern, which are sequentially stacked on the interlayer insulating layer, the second insulating layer pattern having an etch rate lower than that of the first insulating layer pattern.
A fuse region of a semiconductor device, comprising:
- an interlayer insulating layer on a semiconductor substrate;
- a plurality of fuses on the interlayer insulating layer in parallel with each other;
- a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses;
- and
- a plurality of insulating fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer;
- wherein the fuses are exposed down to lower ends of their sidewalls by the insulating fuse grooves.
A fuse region of a semiconductor device, comprising:
- an interlayer insulating layer on a semiconductor substrate;
- a plurality of fuses on the interlayer insulating layer in parallel with each other;
- a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses;
- and
- a plurality of insulating fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer;
- wherein the insulating fuse grooves are unfilled.
Dependencies are inferred from the claim text.