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US 7,352,032 B1Granted
Output driver with split pins
AssigneeNational Semiconductor Corporation
InventorsCharles Chu, Marcel ter Beek
Life of this patent
Estimating the term…
Abstract
The drains of the PMOS transistor and the NMOS transistor of a driver are separated and connected to two spaced-apart pins. The spaced-apart pins provide ESD protection to the NMOS transistor, which can be turned on during an ESD event by voltages that propagate through the PMOS transistor during the ESD event.
Claims20
A semiconductor chip comprising:
- an external surface;
- a plurality of external connection points that touch the external surface, the plurality of external connection points including a first external connection point and a second external connection point, the first and second external connection points being spaced apart;
- and
- a driver having:
- a PMOS transistor having a source connected to a power supply line, a drain connected to the first external connection point, and a gate;
- and
- an NMOS transistor having a source connected to a ground line, a drain connected to the second external connection point, and a gate connected to the gate of the PMOS transistor.
4 more elements
A electrical structure comprising:
- a semiconductor chip having:
- an external surface;
- a plurality of external connection points that touch the external surface, the plurality of external connection points including a first external connection point and a second external connection point, the first and second external connection points being spaced apart;
- and
- a driver having:
- a PMOS transistor having a source connected to a power supply line, a drain connected to the first external connection point, and a gate;
- and
- an NMOS transistor having a source connected to a ground line, a drain connected to the second external connection point, and a gate connected to the gate of the PMOS transistor;
- and
- a printed circuit board having:
- a top surface;
- and
- a number of metal regions that touch the top surface, the first and second external connection points being electrically connected to a single metal region, the drain of the NMOS transistor and the drain of the PMOS transistor being electrically connected together only by way of the single metal region.
10 more elements
A electrical structure comprising:
- a semiconductor chip having:
- an external surface;
- a plurality of external connection points that touch the external surface, the plurality of external connection points including a first external connection point and a second external connection point, the first and second external connection points being spaced apart;
- and
- a driver having:
- a PMOS transistor having a source connected to a power supply line, a drain connected to the first external connection point, and a gate;
- and
- an NMOS transistor having a source connected to a ground line, a drain connected to the second external connection point, and a gate connected to the gate of the PMOS transistor;
- and
- a printed circuit board having:
- a top surface;
- and
- a number of metal regions that touch the top surface, the number of metal regions including a first metal region and a second metal region that is isolated from the first metal region, the first and second external connection points being electrically connected to the first metal region, the drain of the NMOS transistor and the drain of the PMOS transistor being electrically connected together only by way of the first metal region.
10 more elements
Dependencies are inferred from the claim text.