Electrostatic-breakdown-preventive and protective circuit for semiconductor-device
AssigneeOki Electric Industry Co., Ltd.
InventorKatsuhiro Kato
Life of this patent
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Abstract
A compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations includes first and second protective transistors. The distance from a contact hole for connecting an impurity diffusion layer serving as a source and a drain of each of the first and second protective transistors with a metallic wiring, to gates of the protective transistors, is made shorter than a corresponding distance in an output transistor or a protective transistor provided for an input terminal.
Claims4
An electrostatic-breakdown-preventive and protective circuit for a semiconductor-device, the circuit comprising:
- a first protective transistor disposed between a first power-source line and a second power-source line, the first power-source line is connected to one of a first output transistor and a first protection transistor disposed at an input terminal, and the second power-source line is connected to an inverter of an internal circuit;
- and
- a second protective transistor disposed between a first ground line and a second ground line, the first ground line is connected to one of a second output transistor and a second protection transistor disposed at the input terminal, and the second ground line is connected to the inverter of the internal circuit,
- wherein a distance from first contact holes for connecting first impurity diffusion layers which serve as sources and as drains of each of the first and second protective transistors with metallic wiring, to gates of the first and second protective transistors, is smaller than a distance from second contact holes for connecting second impurity diffusion layers which serve as sources and as drains of the respective ones of the first and second output transistors and the first and second protection transistors disposed at the input terminal with metallic wiring, to gates of the first and second output transistors and the first and second protection transistors.
Dependencies are inferred from the claim text.